4-A, 600-V half bridge gate driver
Product details
Parameters
Package | Pins | Size
Features
- High-Side, Low-Side Configuration, with Independent Inputs
- Fully Operational up to 600 V (HS Pin)
- Floating Channel Designed for Bootstrap Operation
- Peak Output Current Capability of 4-A Sink 4-A Source at VDD = 15 V
- Best-In-Class Propagation Delay (125-ns Maximum)
- Best-In-Class Delay Matching (20-ns Maximum)
- TTL and CMOS Compatible Input Logic
- VDD Bias Supply Range of 10 V to 20 V
- Bias UVLO Protection for Both Channels
- Rail-to-Rail Drive
- Robust Operation Under Negative Voltage Transients
- High dv/dt Immunity (HS Pin)
- Separated Grounds for Logic (VSS) and Driver (COM) with Capability to Sustain Voltage Difference
- Optional Enable Function (Pin 4)
- Outputs Held in LOW when Inputs Floating
- Inputs and Enable Pin Voltage Levels Not Restricted by VDD Pin Bias Supply Voltage
- High and Low Voltage Pins Separated for Maximum Creepage and Clearance
- Negative Voltage Handling Capability on Input and Enable Pins
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Description
UCC27714 is a 600-V high-side, low-side gate driver with 4-A source and 4-A sink current capability, targeted to drive power MOSFETs or IGBTs. The device comprises of one ground-referenced channel (LO) and one floating channel (HO) which is designed for operating with bootstrap supplies. The device features excellent robustness and noise immunity with capability to maintain operational logic at negative voltages of up to –8 VDC on HS pin (at VDD = 12 V).
The device accepts a wide range bias supply input from 10 V to 20 V and offers UVLO protection for both the VCC and HB bias supply pins. UCC27714 is available in SOIC-14 package and rated to operate from –40°C to 125°C.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
This 600W EVM was designed to demonstrate how the UCC28950 control IC, UCC27524A and UCC27714 gate drivers could be used in a phase shifted full bridge converter that achieves ZVS from 50 to 100% load.
Features
- ZVS from 50 to 100% load
- Example of High efficiency design for 80 + Applications
- Burst mode/DCM Function to reduce no load power dissipation to meet green mode requirements
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 14 | View options |
Ordering & quality
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- Ongoing reliability monitoring
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