SNVSA88C December   2014  – November 2016 UCC28063A


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Principles of Operation
      2. 8.3.2  Natural Interleaving
      3. 8.3.3  On-Time Control, Maximum Frequency Limiting, and Restart Timer
      4. 8.3.4  Distortion Reduction
      5. 8.3.5  Zero-Current Detection and Valley Switching
      6. 8.3.6  Phase Management and Light-Load Operation
      7. 8.3.7  External Disable
      8. 8.3.8  Improved Error Amplifier
      9. 8.3.9  Soft Start
      10. 8.3.10 Brownout Protection
      11. 8.3.11 Dropout Detection
      12. 8.3.12 VREF
      13. 8.3.13 VCC
      14. 8.3.14 Control of Downstream Converter
      15. 8.3.15 System Level Protections
        1. Failsafe OVP - Output Overvoltage Protection
        2. Overcurrent Protection
        3. Open-Loop Protection
        4. VCC Undervoltage Lock-Out (UVLO) Protection
        5. Phase-Fail Protection
        6. Thermal Shutdown Protection
        7. AC-Line Brownout and Dropout Protections
        8. Fault Logic Diagram
    4. 8.4 Device Functional Modes
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Inductor Selection
        2.  ZCD Resistor Selection (RZA, RZB)
        3.  HVSEN
        4.  Output Capacitor Selection
        5.  Selecting (RS) For Peak Current Limiting
        6.  Power Semiconductor Selection (Q1, Q2, D1, D2)
        7.  Brownout Protection
        8.  Converter Timing
        9.  Programming VOUT
        10. Voltage Loop Compensation
      3. 9.2.3 Application Curves
        1. Input Ripple Current Cancellation with Natural Interleaving
        2. Brownout Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. Related Parts
      2. 12.1.2 Device Nomenclature
        1. Detailed Pin Description
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Applications and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

This control IC is generally applicable to the control of AC-DC power supplies which require Active Power Factor Correction off Universal AC line. Applications using this IC will generally meet the Class D equipment input current harmonics standards per EN61000-3-2. This standard applies to equipment with rated Powers higher than 75W. The IC brings two phase interleaved control capability to the Transition Mode Boost and hence will be generally a very good choice for cost optimized applications in the 150W to 800W space, or to even lower powers that wish to exploit the interleaving benefits of reduced filtering component size, lower profile solutions and distributed thermal management.

The UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator User's Guide (SLUU512) describes an EVM design for a 300W Application.

This EVM has an associated Excel file to help automate calculations for its component choices available at SLUC292.

Typical Application

An example of the UCC28063A PFC controller in a two-phase interleaved, transition-mode PFC pre-regulator is shown in .

UCC28063A fig10_snvsa88.gif Figure 34. Typical Interleaved Transition-Mode PFC Pre-Regulator

Design Requirements

The specifications for this design were chosen based on the power requirements of a typical 300-W LCD TV. These specifications are shown in Table 2.

Table 2. Design Specifications

VIN RMS input voltage 85 (VIN_MIN) 265 (VIN_MAX) VRMS
VOUT Output voltage 390 V
fLINE AC-line frequency 47 63 Hz
PF Power factor at maximum load 0.90
POUT 300 W
η Full-load efficiency 92%
fMIN Minimum switching frequency 45 kHz

Detailed Design Procedure

Inductor Selection

The boost inductor is selected based on the inductor ripple current requirements at the peak of low line. Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (DPEAK_LOW_LINE), as shown in Equation 18.

Equation 18. UCC28063A qu18_lusao7.gif

The minimum switching frequency of the converter (fMIN) under low line conditions occurs at the peak of low line and is set between 25 kHz and 50 kHz to avoid audible noise. For this design example, fMIN is set to 45 kHz. For a 2-phase interleaved design, L1 and L2 are determined as shown in Equation 19.

Equation 19. UCC28063A qu19_lusao7.gif

The inductor for this design would have a peak current (ILPEAK) of 5.4 A, as shown in Equation 20, and an RMS current (ILRMS) of 2.2 A, as shown in Equation 21.

Equation 20. UCC28063A qu20_lusao7.gif
Equation 21. UCC28063A qu21_lusao7.gif

This converter uses constant on time (TON) and zero-current detection (ZCD) to set up the converter timing. Auxiliary windings on L1 and L2 detect when the inductor currents are zero. Selecting the turns ratio using Equation 22 ensures that there will be at least 2 V at the peak of high line to reset the ZCD comparator after every switching cycle.

The turns-ratio of each auxiliary winding is:

Equation 22. UCC28063A qu22_lusao7.gif

ZCD Resistor Selection (RZA, RZB)

The minimum value of the ZCD resistors is selected based on the internal clamps maximum current ratings of 3 mA, as shown in Equation 23.

Equation 23. UCC28063A qu23_lusao7.gif

In this design the ZCD resistors are set to 20 kΩ, as shown in Equation 24.

Equation 24. UCC28063A qu24_lusao7.gif


The HVSEN pin programs the PWMCNTL output of the UCC28063A. The PWMCNTL open-drain output can be used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts high impedance and pulls to ground when HVSEN increases above 2.5 V. Setting the point where PWMCNTL becomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 25 to Equation 30 show how to set the PWMCNTL pin to activate when the output voltage is within 90% of its nominal value.

Equation 25. UCC28063A qu25_lusao7.gif

Resistor RE sets up the high side of the voltage divider and programs the hysteresis of the PWMCNTL signal. For this example, RE was selected to provide 99 V of hysteresis, as shown in Equation 26. Three resistors in series were used to meet voltage requirements.

Equation 26. UCC28063A qu26_lusao7.gif

Resistor RF is used to program the PWMCNTL active threshold, as shown in Equation 27.

Equation 27. UCC28063A qu27_lusao7.gif

Select a standard resistor value for RF.

Equation 28. UCC28063A qu28_lusao7.gif

This PWMCNTL output will remain active until a minimum output voltage (VOUT_MIN) is reached, as shown in Equation 29.

Equation 29. UCC28063A qu29_lusao7.gif

According to these resistor values, the FailSafe OVP threshold will be set according to Equation 30

Equation 30. UCC28063A qu30_lusao7.gif

Output Capacitor Selection

The output capacitor (COUT) is selected based on holdup requirements, as shown in Equation 31.

Equation 31. UCC28063A qu31_lusao7.gif

Two 100-μF capacitors were used in parallel for the output capacitor.

Equation 32. UCC28063A qu32_lusao7.gif

For this size capacitor, the low-frequency peak-to-peak output voltage ripple (VRIPPLE) is approximately 14 V, as shown in Equation 33:

Equation 33. UCC28063A qu33_lusao7.gif

In addition to holdup requirements, a capacitor must be selected so that it can withstand the low-frequency RMS current (ICOUT_100Hz) and the high-frequency RMS current (ICOUT_HF); see Equation 34 to Equation 36. High-voltage electrolytic capacitors generally have both a low- and a high-frequency RMS current ratings on the product data sheets.

Equation 34. UCC28063A qu34_lusao7.gif
Equation 35. UCC28063A qu35_lusao7.gif
Equation 36. UCC28063A qu36_lusao7.gif

Selecting (RS) For Peak Current Limiting

The UCC28063A peak limit comparator senses the total input current and is used to protect the MOSFETs during inrush and over-load conditions. For reliability, the peak current limit (IPEAK) threshold in this design is set for 120% of the nominal maximum current that will be observed during power up, as shown in Equation 37.

Equation 37. UCC28063A qu37_lusao7.gif

A standard 15-mΩ metal-film current-sense resistor will be used for current sensing, as shown in Equation 38. The estimated power loss of the current-sense resistor (PRS) is less than 0.25 W during normal operation, as shown in Equation 39.

Equation 38. UCC28063A qu38_lusao7.gif
Equation 39. UCC28063A qu39_lusao7.gif

The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to withstand a short-circuit current larger than the current required to open the fuse (F1). I2t (ampere-squared- seconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I2t is equal to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I2t of 14 A2s was chosen to protect the design from a short-circuit condition. To ensure the current-sense resistor has high-enough surge protection, a 15-mΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a 2.5-W surge rating for 5 seconds. This result translates into 833 A2s and has a high-enough I2t rating to survive a short-circuit before the fuse opens, as described in Equation 40.

Equation 40. UCC28063A qu40_lusao7.gif

Power Semiconductor Selection (Q1, Q2, D1, D2)

The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application Note SLUU138, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator, explains how to select power semiconductor components for transition-mode PFC pre-regulators.

The MOSFET (Q1, Q2) pulsed-drain maximum current is shown in Equation 41:

Equation 41. UCC28063A qu41_lusao7.gif

The MOSFET (Q1, Q2) RMS current calculation is shown in Equation 42:

Equation 42. UCC28063A qu42_lusao7.gif

To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.

The boost diode (D1, D2) RMS current is shown in Equation 43:

Equation 43. UCC28063A qu43_lusao7.gif

To meet the power requirements of the design, MURS360T3, 600-V diodes were chosen for D1 and D2.

Brownout Protection

Resistor RA and RB are selected to activate brownout protection at ~75% of the specified minimum-operating input voltage. Resistor RA programs the brownout hysteresis comparator, which is selected to provide 17 V (~12 VRMS) of hysteresis. Calculations for RA and RB are shown in Equation 44 through Equation 47.

Equation 44. UCC28063A qu44_lusao7.gif

To meet voltage requirements, three 2.87-MΩ resistors were used in series for RA.

Equation 45. UCC28063A qu45_lusao7.gif
Equation 46. UCC28063A qu46_lusao7.gif

Select a standard value for RB.

Equation 47. UCC28063A qu47_lusao7.gif

In this design example, brownout becomes active (shuts down PFC) when the input drops below 66 VRMS for longer than 440 ms and deactivates (restarts with a full soft start) when the input reaches 78 VRMS.

Converter Timing

The maximum on-time TON depends on fMIN as determined by Equation 48. To ensure proper operation, the timing must be set based on the highest boost inductance (L1MAX) and output power (POUT). In this design example, the boost inductor could be as high as 390 µH. Calculate the timing resistor RT as shown in Equation 49.

Equation 48. UCC28063A qu48_lusao7.gif
Equation 49. UCC28063A qu49_lusao7.gif

This result sets the maximum frequency clamp (fMAX), as shown in Equation 50, which improves efficiency at light load.

Equation 50. UCC28063A qu50_lusao7.gif

Programming VOUT

Resistor RC is selected to minimize loading on the power line when the PFC is disabled. Construct resistor RC from two or more resistors in series to meet high-voltage requirements. Resistor RD is then calculated based on RC, the reference voltage, VREF, and the required output voltage, VOUT. Based on the values shown in Equation 51 to Equation 54, the primary output over-voltage protection threshold should be as shown in Equation 55:

Equation 51. UCC28063A qu51_lusao7.gif
Equation 52. UCC28063A qu52_lusao7.gif
Equation 53. UCC28063A qu53_lusao7.gif

Select a standard value for RD.

Equation 54. UCC28063A qu54_lusao7.gif
Equation 55. UCC28063A qu55_lusao7.gif

Voltage Loop Compensation

Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This value ensures good power factor and low harmonic distortion on the input current.

The transconductance amplifier small-signal gain is shown in Equation 56:

Equation 56. UCC28063A qu56_lusao7.gif

The voltage-divider feedback gain is shown in Equation 57:

Equation 57. UCC28063A qu57_lusao7.gif

The value of RZ is calculated as shown in Equation 58:

Equation 58. UCC28063A qu58_lusao7.gif

CZ is then set to add 45° phase margin at 1/5th of the line frequency, as shown in Equation 59:

Equation 59. UCC28063A qu59_lusao7.gif

CP is sized to attenuate high-frequency switching noise, as shown in Equation 60:

Equation 60. UCC28063A qu60_lusao7.gif

Standard values should be chosen for RZ, CZ and CP, as shown in Equation 61 to Equation 63.

Equation 61. UCC28063A qu61_lusao7.gif
Equation 62. UCC28063A qu62_lusao7.gif
Equation 63. UCC28063A qu63_lusao7.gif

Application Curves

Refer to UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator EVM User's Guide, SLUU512, for more implementation details and application curves.

Input Ripple Current Cancellation with Natural Interleaving

Figure 35 through Figure 37 show the input current (M1= IL1 + IL2), Inductor Ripple Currents (IL1, IL2) versus rectified line voltage. From these graphs, it can be observed that natural interleaving reduces the overall magnitude of input (and output) ripple current caused by the individual inductor current ripples.

UCC28063A ai_tc_ripple02_luu280.gif Figure 35. Inductor and Input Ripple Current at 85 VRMS at Peak of Line Voltage
UCC28063A ai_tc_pout1_luu280.gif Figure 37. Inductor and Input Ripple Current at VIN = 85 VRMS, POUT = 300 W
UCC28063A ai_tc_ripple04_luu280.gif Figure 36. Inductor and Input Ripple Current at 265 VRMS Input at Peak Line Voltage

Brownout Protection

The UCC28063A has a brownout protection that shuts down both gate drives (GDA and GDB) when the VINAC pin detects that the RMS input voltage is too low. This EVM was designed to go into a brownout state when the line drops below 64 VRMS. Once the UCC28063A control device has determined that the input is in a brownout condition, a 400-ms timer starts to allow the line to recover before shutting down the gate drivers. After 400 ms of brownout, both gate drivers turn off, as shown in Figure 38.

UCC28063A ai_tc_brownout02_luu280.gif Figure 38. UCC28063A Response to a Line Brownout Event at 265 VRMS