SNVSA88C December 2014 – November 2016 UCC28063A
Table 3 lists several TI parts that have characteristics similar to the UCC28063A.
|UCC28050/51||Transition-mode PFC controller for low to medium power applications|
|UCC28019||8-pin continuous-conduction-mode (ccm) pfc controller (with slew-rate correction current)|
|UCC28019A||8-pin continuous-conduction-mode (ccm) pfc controller (with 2-level voltage-error gain)|
|UCC28060||Two-phase interleaved transition-mode pfc controller (with input voltage range gain change)|
|UCC28061||Two-phase interleaved transition-mode pfc controller (with no input voltage gain change)|
|UCC28070||Two-phase interleaved ccm (average current mode) pfc controller|
|UCC28063||Two-phase interleaved transition-mode pfc controller (with improved audible noise)|
Analog Ground: Connect analog signal bypass capacitors, compensation components, and analog signal returns to this pin. Connect the analog and power grounds at a single point to isolate high-current noise signals of the power components from interference with the low-current analog circuits.
Error Amplifier Output: The error amplifier is a transconductance amplifier, so this output is a high-impedance current source. Connect voltage-regulation loop-compensation components from this pin to AGND. The on-time seen at the gate-drive outputs is proportional to the voltage at this pin minus an offset of approximately 125 mV. During normal operation, the error amplifier maintains a transconductance of 55 μS for small-signal disturbances on VSENSE, and shifts to ~290 μS when VSENSE deviates more than ±5% from VSENSEreg. During an AC-line Dropout condition, the error amplifier output is disabled and an internal 4-μA source discharges COMP for the duration of the Dropout condition. During a VSENSE-based OV event, an internal 2-kΩ resistor is applied from COMP to GND until the OV condition clears. During soft-start triggering events (UVLO, Disable, Brownout, HVSEN over-voltage, or Thermal Shutdown), the error-amp output is disabled and COMP is pulled low by an internal 2-kΩ resistor. The soft-start condition begins only after the triggering event clears and COMP has been discharged below 20 mV, ensuring that the circuit restarts with a low COMP voltage and a short on-time. (Do not connect COMP to a low-impedance source that would interfere with COMP falling below 20 mV.) During Soft-Start, the error amplifier high transconductance is enabled and COMP current is -125 μA as long as VSENSE < VREF/2. Once VSENSE exceeds VREF/2, the high gain is disabled and only the small-signal gain capability is available with a maximum COMP current of approximately –16 μA. Normal operation resumes once VSENSE > 0.983VREF (~5.9 V).
Current Sense Input: Connect the current-sense resistor and the negative terminal of the diode bridge to this pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As input current increases, the voltage on CS will go more negative. This cycle-by-cycle over-current protection limits input current by turning off both gate driver outputs (GDx) when CS is more negative than the CS rising threshold (approximately -200 mV in two-phase operation and approximately -167 mV in single-phase and phase-fail condition). The gate drive outputs will remain low until CS falls to the CS falling threshold (approx. -15 mV). Current sense is blanked for approximately 100 ns following the rising and falling edge of either GDx output. This filters noise that may occur from gate-drive current or when inductor current switches from a power FET to a boost diode. In most cases, no additional current sense filtering is required. If external filtering is deemed necessary, or to prevent excessive negative voltage on the CS pin during AC-inrush conditions, a series resistor is recommended to connect the current sensing resistor to the CS pin. Due to the CS bias current, this external resistor should be less than 100 Ω to maintain accuracy.
Channel A and Channel B Gate Drive Output: Connect these pins to the gate of the power FET for each phase through the shortest connection practicable. If it is necessary to use a trace longer than 0.5 inch (12.6 mm) for this connection, some ringing may occur due to trace series inductance. This ringing can be damped by adding a low-value resistor in series with GDA and GDB.
High Voltage Output Sense: The UCC28063A incorporates FailSafe OVP so that any single failure does not allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and HVSEN but their actions are different if either pin exceeds their respective over-voltage thresholds. Using two pins to monitor for over-voltage provides redundant protection and fault tolerance. When HVSEN exceeds its over-voltage threshold, it triggers a full soft-start of the controller. HVSEN can also be used to enable a downstream power converter when the voltage on HVSEN is within the operating region. When HVSEN is greater than 2.5 V, the PWMCNTL output may be driven Low (provided no other fault exists). When HVSEN falls below 2.5 V, the PWMCNTL output becomes high-impedance. Select the HVSEN divider ratio for the desired over-voltage and power-good thresholds. Select the HVSEN divider impedance for the desired power-good hysteresis based on the hysteresis current. During operation, HVSEN must never fall below 0.8 V. Dropping HVSEN below 0.8 V puts the UCC28063A into a special test mode, used only for factory testing. A bypass capacitor from HVSEN to AGND is recommended to filter noise and avoid false over-voltage shutdown.
Phase-B Enable/Disable: When the voltage applied to this pin is below the Phase-B enable threshold, Phase B of the boost converter and the Phase Fail detector are disabled. The commanded on-time for Phase A is immediately doubled when Phase B is disabled, which helps keep COMP voltage constant during the phase-management transient. The PHB pin allows the user to add external phase-management control circuitry, if desired. To disable phase-management, connect the PHB pin to the VREF pin.
PWM-Control Output: This open-drain output goes low when HVSEN is within the HVSEN-good region (HVSEN > 2.5 V), there is no FailSafe OV, and there is no Phase-Fail condition when operating in two-phase mode (see PHB pin). Otherwise, PWMCNTL is high-impedance.
Timing Set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus COMP voltage and the minimum switching period at the gate-drive outputs.
Bias Supply Input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect a 0.1-μF or larger ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This bias supply powers all circuits within the device and must be capable of delivering the steady-state dc current plus the transient power-MOSFET gate-charging current. Input bias current is very low during undervoltage-lockout (UVLO) or stand-by conditions (VSENSE < 1.25 V).
Input AC Voltage Sense: For normal operation, connect this pin to a voltage divider across the rectified input power mains. When the voltage on VINAC remains below the brownout threshold for longer than the brownout filter time, the device enters a brownout mode, both output drivers are disabled and a full soft-start is triggered. Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the desired brownout hysteresis based on the hysteresis current. A dropout condition is triggered when VINAC remains below the dropout threshold for longer than the dropout filter time. The error amplifier is disabled and an internal 4-μA current source discharges COMP for the duration of the dropout condition. The dropout condition is immediately cleared and normal operation resumes when VINAC exceeds the dropout-clear threshold.
Voltage Reference Output: Connect a 0.1-μF or larger ceramic bypass capacitor from this pin to AGND. VREF turns off during UVLO and VSENSE-disable to save bias current and increase stand-by efficiency. This reference output can be used to bias other circuits requiring less than a few milliamperes of non-pulsing total supply current.
Output DC Voltage Sense: Connect this pin to a voltage divider across the output of the power converter. In a closed-loop system, the voltage at VSENSE is regulated to the error amplifier reference voltage. Select the output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to analog ground (AGND) through a separate short trace for best output regulation accuracy and noise immunity. Controller operation may be enabled when VSENSE voltage exceeds the 1.25-V enable threshold. VSENSE can be pulled low by an open-drain logic output, or >6-V logic output in series with a low-leakage diode, to disable the outputs and reduce VCC current. Two levels of output overvoltage are detected at this input. If VSENSE exceeds the first-level overvoltage protection threshold VLOW_OV, an internal 2-kΩ resistor is applied to COMP to quickly reduce gate-drive on-time. If VSENSE continues to rise past the second-level threshold VHIGH_OV, GDA and GDB are immediately latched off. This latch is cleared when VSENSE falls below the OV-clear threshold. If VSENSE becomes disconnected, open-loop protection provides an internal current source to pull VSENSE low, which disables the controller and triggers a soft-start condition.
Zero Current Detection Inputs: These inputs are used to detect a negative-going edge when the boost inductor current in each respective phase goes to zero. The inputs are clamped between 0 V and 3 V. Connect each pin through a current limiting resistor to the zero-crossing detection (ZCD) winding of the corresponding boost inductor. The resistor value should be chosen to limit the clamping currents to less than ±3 mA. The inductor winding polarity must be arranged so that this ZCD voltage falls when the inductor current decays to zero. When the inductor current falls to zero, the ZCD input must drop below the falling threshold (approximately 1 V) to cause the gate drive output to rise. Subsequently, when the power-MOSFET turns off, the ZCD input must rise above the rising threshold (approximately 1.7 V) to arm the logic for another falling ZCD edge.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.