SGLS187C September   2003  – August 2025 UCC2808A-1EP , UCC2808A-2EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Pin Descriptions
        1. 7.3.1.1 COMP
        2. 7.3.1.2 CS
        3. 7.3.1.3 FB
        4. 7.3.1.4 GND
        5. 7.3.1.5 OUTA and OUTB
        6. 7.3.1.6 RC
        7. 7.3.1.7 VDD
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC
      2. 7.4.2 Push-Pull or Half-Bridge Function
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = –40°C to +125°C for the UCC2808A-xEP, VDD = 10V(1), 1µF capacitor from VDD to GND, R = 22kΩ, C = 330pF, and TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCILLATOR
Oscillator frequency 175 194 213 kHz
Oscillator amplitude/VDD(2) 0.44 0.5 0.56 V/V
ERROR AMPLIFIER
Input voltage COMP = 2V 1.95 2 2.05 V
Input bias current –1 1 µA
Open loop voltage gain 60 80 dB
COMP sink current FB = 2.2V, COMP = 1V 0.3 2.5 mA
COMP source current FB = 1.3V, COMP = 3.5V –0.2 –0.5 mA
PWM
Maximum duty cycle Measured at OUTA or OUTB 48% 49% 50%
Minimum duty cycle COMP = 0V 0%
CURRENT SENSE
Gain(3) 1.9 2.2 2.5 V/V
Maximum input signal COMP = 5V(4) 0.45 0.5 0.55 V
CS to output delay COMP = 3.5V, CS from 0mV to 600mV 100 200 ns
CS source current –200 nA
CS sink current CS = 0.5V, RC = 5.5V(5) 4 10 mA
Over current threshold 0.65 0.75 0.85 V
COMP to CS offset CS = 0V 0.35 0.8 1.2 V
OUTPUT
OUT low level I = 100mA 0.5 1.1 V
OUT high level I = –50mA, VDD – OUT 0.5 1 V
Rise time CL = 1nF 25 60 ns
Fall time CL = 1nF 25 60 ns
UNDERVOLTAGE LOCKOUT
Start threshold UCC2808A-1EP(1) 11.5 12.5 13.5 V
UCC2808A-2EP 4.1 4.3 4.5
Minimum operating voltage after start UCC2808A-1EP 7.6 8.3 9 V
UCC2808A-2EP 3.9 4.1 4.3
Hysteresis UCC2808A-1EP 3.5 4.2 5.1 V
UCC2808A-2EP 0.1 0.2 0.3
SOFT START
COMP rise time FB = 1.8V, rise from 0.5V to 4V 3.5 20 ms
OVERALL
Start-up current VDD < start threshold 130 260 µA
Operating supply current FB = 0V, CS = 0V(1)(6) 1 2 mA
VDD zener shunt voltage IDD = 10mA(7) 13 14 15 V
(1) For UCC2808A-1EP, set VDD above the start threshold before setting at 10V.
(2) Measured at RC. Signal amplitude tracks VDD.
(3) Gain is defined by: A = ΔVCOMP / ΔVCS, 0V ≤ VCS ≤ 0.4V.
(4) Parameter measured at trip point of latch with FB at 0V.
(5) The internal current sink on the CS pin is designed to discharge an external filter capacitor, and is not intended to be a DC sink path.
(6) Does not include current in the external oscillator network.
(7) Start threshold and zener shunt threshold track together.