SGLS187C September   2003  – August 2025 UCC2808A-1EP , UCC2808A-2EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Pin Descriptions
        1. 7.3.1.1 COMP
        2. 7.3.1.2 CS
        3. 7.3.1.3 FB
        4. 7.3.1.4 GND
        5. 7.3.1.5 OUTA and OUTB
        6. 7.3.1.6 RC
        7. 7.3.1.7 VDD
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC
      2. 7.4.2 Push-Pull or Half-Bridge Function
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 UCC2808A-xEP: D Package, 8-Pin SOIC (Top View)
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
COMP 1 O COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier in the UCC2808A-xEP is a true low-output impedance, 2MHz operational amplifier. As such, the COMP pin both sources and sinks current. However, the error amplifier is internally current limited, so that zero duty cycle is externally forced by pulling COMP to GND. The UCCx808A family features built-in full-cycle soft start. Soft start is implemented as a clamp on the maximum COMP voltage.
CS 3 I The input to the PWM, peak current, and overcurrent comparators. The overcurrent comparator is only intended for fault sensing. Exceeding the overcurrent threshold causes a soft-start cycle. An internal MOSFET discharges the current sense filter capacitor to improve dynamic performance of the power converter.
FB 2 I The inverting input to the error amplifier. For best stability, keep FB lead length as short as possible and FB stray capacitance as small as possible.
GND 5 G Reference ground and power ground for all functions. Because of high currents, and high-frequency operation of the UCC2808A-xEP, a low-impedance circuit board ground plane is highly recommended.
OUTA 7 O Alternating high current output stages. Both stages are capable of driving the gate of a power MOSFET. Each stage is capable of 500mA peak-source current and 1A peak-sink current. The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two outputs, along with a slower output rise time than fall time, prevents the two outputs from simultaneous activity. This dead time is typically 60ns to 200ns and depends upon the values of the timing capacitor and resistor. The high-current-output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output stage also provides a very low impedance to overshoot and undershoot. This configuration means that in many cases, external Schottky-clamp diodes are not required.
OUTB 6 O Alternating high current output stages. Both stages are capable of driving the gate of a power MOSFET. Each stage is capable of 500mA peak-source current and 1A peak-sink current. The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the RC pin is rising, one of the two outputs is high. During fall time, both outputs are off. The dead time between the two outputs and a slower output rise time than fall time, prevents the two outputs from simultaneous activity. This dead time is typically 60ns to 200ns and depends upon the values of the timing capacitor and resistor. The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output stage also provides a very low impedance to overshoot and undershoot. This configuration means that in many cases, external Schottky-clamp diodes are not required.
RC 4 O The oscillator programming pin. The UCC2808A-xEP oscillator tracks VDD and GND internally so that variations in power supply rails minimally affect frequency stability. Section 7.2 shows the oscillator block diagram. Only two components are required to program the oscillator: a resistor (tied to the VDD and RC), and a capacitor (tied to the RC and GND). The approximate oscillator frequency is calculated in Section 7.3.1.6.
The recommended range of timing resistors is between 10kΩ and 200kΩ and range of timing capacitors is from 100pF to 1000pF. Avoid timing resistors smaller than 10kΩ. For best performance, keep the timing capacitor lead to GND as short as possible, the timing resistor lead from VDD as short as possible, and the leads between timing components and RC as short as possible. Separate ground and VDD traces to the external timing network are encouraged.
VDD 8 P The power input connection for this device. Although quiescent VDD current is very low, total supply current is higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current is calculated in Section 7.3.1.7. To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along with an electrolytic capacitor. A 1µF decoupling capacitor is recommended.
(1) P = Power, G = Ground, I = Input, O = Output