SLUSBQ5D November   2013  – July 2016 UCC28180


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Soft Start
      2. 8.3.2  System Protection
      3. 8.3.3  VCC Undervoltage LockOut (UVLO)
      4. 8.3.4  Output Overvoltage Protection (OVP)
      5. 8.3.5  Open Loop Protection/Standby (OLP/Standby)
      6. 8.3.6  ISENSE Open-Pin Protection (ISOP)
      7. 8.3.7  ICOMP Open-Pin Protection (ICOMPP)
      8. 8.3.8  FAULT Protection
      9. 8.3.9  Output Overvoltage Detection (OVD), Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)
      10. 8.3.10 Overcurrent Protection
      11. 8.3.11 Soft Overcurrent (SOC)
      12. 8.3.12 Peak Current Limit (PCL)
      13. 8.3.13 Current Sense Resistor, RISENSE
      14. 8.3.14 ISENSE Pin
      15. 8.3.15 Gate Driver
      16. 8.3.16 Current Loop
      17. 8.3.17 ISENSE and ICOMP Functions
      18. 8.3.18 Pulse Width Modulator
      19. 8.3.19 Control Logic
      20. 8.3.20 Voltage Loop
      21. 8.3.21 Output Sensing
      22. 8.3.22 Voltage Error Amplifier
      23. 8.3.23 Non-Linear Gain Generation
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Current Calculations
        2.  Switching Frequency
        3.  Bridge Rectifier
        4.  Inductor Ripple Current
        5.  Input Capacitor
        6.  Boost Inductor
        7.  Boost Diode
        8.  Switching Element
        9.  Sense Resistor
        10. Output Capacitor
        11. Output Voltage Set Point
        12. Loop Compensation
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Bias Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support . .
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC28180 is a switch-mode controller used in boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. The UCC28180 requires few external components to operate as an active PFC pre-regulator. The operating switching frequency can be programmed from 18 kHz to 250 kHz simply by connecting the FREQ pin to ground through a resistor.

The internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide 85-VAC to 265-VAC mains input range from zero to full output load. The usable system load ranges from 100 W to few kW.

Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the sinusoidal input voltage under continuous inductor current conditions. Under light-load conditions, depending on the boost inductor value, the inductor current may go discontinuous but still meet Class-A/D requirements of IEC 61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by generating a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gain parameters for maintaining a low-distortion, steady-state, input-current wave shape.

9.2 Typical Application

UCC28180 fig1_slusbq5.gif Figure 29. Design Example Schematic

9.2.1 Design Requirements

This example illustrates the design process and component selection for a continuous mode power factor correction boost converter utilizing the UCC28180. The pertinent design equations are shown for a universal input, 360-W PFC converter with an output voltage of 390 V.

Table 1. Design Goal Parameters

VIN Input voltage 85 265 VAC
fLINE Input frequency 47 63 Hz
IIN(peak) Peak input current VIN = VIN(min),
IOUT = IOUT(max)
7 A
VOUT Output voltage VIN(min) ≤ VIN ≤ VIN(max),
fLINE(min) ≤ fLINE≤ fLINE(max),
IOUT ≤ IOUT(max)
379 390 402 VDC
Line Regulation VIN(min) ≤ VIN≤ VIN(max),
IOUT = IOUT(max)
Load Regulation VIN = 115 VAC,
fLINE = 60 Hz,
IOUT(min) ≤ IOUT ≤ IOUT(max)
VIN = 230 VAC,
fLINE = 60 Hz,
IOUT(min)≤ IOUT ≤ IOUT(max)
IOUT Output Load Current VIN(min) ≤ VIN ≤ VIN(max)
fLINE(min) ≤ fLINE ≤ fLINE(max)
0 0.923 A
POUT Output Power VIN(min) ≤ VIN ≤ VIN(max)
fLINE(min) ≤ fLINE ≤ fLINE(max)
0 360 W
VRIPPLE(SW) High frequency
Output voltage ripple
VIN = 115 VAC,
fLINE = 60 Hz
IOUT = IOUT(max)
2.5 3.9 VP-P
VIN = 230 VAC,
fLINE = 50 Hz
IOUT = IOUT(max)
2.5 3.9
VRIPPLE(f_LINE) Line frequency
Output voltage ripple
VIN = 115 VAC,
fLINE = 60 Hz,
IOUT = IOUT(max)
11.6 19.5 VP-P
VIN = 230 VAC,
fLINE = 50 Hz,
IOUT = IOUT(max)
13.3 19.5
VOUT(OVP) Output overvoltage protection 425 V
VOUT(UVP) Output undervoltage protection 370
fSW Switching frequency TJ = 25°C 114 120 126 kHz
f(CO) Voltage Loop Bandwidth VIN = 162 VDC,
IOUT = 0.466 A
8 Hz
Voltage Loop Phase Margin VIN = 162 VDC,
IOUT = 0.466 A
68 °
PF Power Factor VIN = 115 VAC,
IOUT = IOUT(max)
THD Total harmonic distortion VIN = 115 VAC,
fLINE = 60 Hz,
IOUT = IOUT(max)
4.3% 10%
VIN = 230 VAC,
fLINE = 50 Hz
IOUT = IOUT(max)
4% 10%
η Full load efficiency VIN = 115 VAC,
fLINE = 60 Hz,
IOUT = IOUT(max)
Ambient temperature 25 °C

9.2.2 Detailed Design Procedure Current Calculations

The input fuse, bridge rectifier, and input capacitor are selected based upon the input current calculations. First, determine the maximum average output current, IOUT(max):

Equation 4. UCC28180 qu1_de_lusbq5.gif
Equation 5. UCC28180 qu2_de_lusbq5.gif

The maximum input RMS line current, IIN_RMS(max), is calculated using the parameters from Table 1 and the efficiency and power factor initial assumptions:

Equation 6. UCC28180 qu3_de_lusbq5.gif
Equation 7. UCC28180 qu4_de_lusbq5.gif

Based upon the calculated RMS value, the maximum input current, IIN (max), and the maximum average input current, IIN_AVG(max), assuming the waveform is sinusoidal, can be determined.

Equation 8. UCC28180 qu5_de_lusbq5.gif
Equation 9. UCC28180 qu6_de_lusbq5.gif
Equation 10. UCC28180 qu7_de_lusbq5.gif
Equation 11. UCC28180 qu8_de_lusbq5.gif Switching Frequency

The UCC28180 switching frequency is user programmable with a single resistor on the FREQ pin to ground. For this design, the switching frequency, fSW, was chosen to be 120 kHz. Figure 30 (same as Figure 1) could be used to select the suitable resistor to program the switching frequency or the value can be calculated using constant scaling values of fTYP and RTYP. In all cases, fTYP is a constant that is equal to 65 kHz, RINT is a constant that is equal to 1 MΩ, and RTYP is a constant that is equal to 32.7 kΩ. Simply applying the calculation below yields the appropriate resistor that should be placed between FREQ and GND:

Equation 12. UCC28180 qu9_de_lusbq5.gif
Equation 13. UCC28180 qu10_de_lusbq5.gif

A typical value of 17.8 kΩ for the FREQ resistor results in a switching frequency of 118 kHz.

UCC28180 C001_SLUSBQ5.png Figure 30. Frequency vs. RFREQ Bridge Rectifier

The input bridge rectifier must have an average current capability that exceeds the input average current. Assuming a forward voltage drop, VF_BRIDGE, of 1 V across the rectifier diodes, BR1, the power loss in the input bridge, PBRIDGE, can be calculated:

Equation 14. UCC28180 qu11_de_lusbq5.gif
Equation 15. UCC28180 qu12_de_lusbq5.gif

Heat sinking will be required to maintain operation within the bridge rectifier’s safe operating area. Inductor Ripple Current

The UCC28180 is a Continuous Conduction Mode (CCM) controller but if the chosen inductor allows relatively high-ripple current, the converter will be forced to operate in Discontinuous Mode (DCM) at light loads and at the higher input voltage range. High-inductor ripple current has an impact on the CCM/DCM boundary and results in higher light-load THD, and also affects the choices for the input capacitor, RSENSE and CICOMP values. Allowing an inductor ripple current, ΔIRIPPLE, of 20% or less will result in CCM operation over the majority of the operating range but requires a boost inductor that has a higher inductance value and the inductor itself will be physically large. As with all converter designs, decisions must be made at the onset in order to optimize performance with size and cost. In this design example, the inductor is sized in such a way as to allow a greater amount of ripple current in order to minimize space with the understanding that the converter operates in DCM at the higher input voltages and at light loads but optimized for a nominal input voltage of 115 VAC at full load. Although specifically defined as a CCM controller, the UCC28180 is shown in this application to meet the overall performance goals while transitioning into DCM at high-line voltage, at a higher load level. Input Capacitor

The input capacitor must be selected based upon the input ripple current and an acceptable high frequency input voltage ripple. Allowing an inductor ripple current, ΔIRIPPLE, of 40% and a high frequency voltage ripple factor, ΔVRIPPLE_IN, of 7%, the maximum input capacitor value, CIN, is calculated by first determining the input ripple current, IRIPPLE, and the input voltage ripple, VIN_RIPPLE:

Equation 16. UCC28180 qu13_de_lusbq5.gif
Equation 17. UCC28180 qu14_de_lusbq5.gif
Equation 18. UCC28180 qu15_de_lusbq5.gif
Equation 19. UCC28180 qu16_de_lusbq5.gif
Equation 20. UCC28180 qu17_de_lusbq5.gif
Equation 21. UCC28180 qu18_de_lusbq5.gif
Equation 22. UCC28180 qu19_de_lusbq5.gif
Equation 23. UCC28180 qu20_de_lusbq5.gif

The recommended value for the input x-capacitor can now be calculated:

Equation 24. UCC28180 qu21_de_lusbq5.gif
Equation 25. UCC28180 qu22_de_lusbq5.gif

A standard value 0.33-µF Y2/X2 film capacitor is used. Boost Inductor

Based upon the allowable inductor ripple current discussed above, the boost inductor, LBST, is selected after determining the maximum inductor peak current, IL_PEAK:

Equation 26. UCC28180 qu23_de_lusbq5.gif
Equation 27. UCC28180 qu24_de_lusbq5.gif

The minimum value of the boost inductor is calculated based upon the acceptable ripple current, IRIPPLE, at a worst case duty cycle of 0.5:

Equation 28. UCC28180 qu25_de_lusbq5.gif
Equation 29. UCC28180 qu26_de_lusbq5.gif

The recommended minimum value for the boost inductor assuming a 40% ripple current is 321 µH; the actual value of the boost inductor that will be used is 327 µH. With this actual value used, the actual resultant inductor current ripple will be:

Equation 30. UCC28180 qu27_de_lusbq5.gif
Equation 31. UCC28180 qu28_de_lusbq5.gif
Equation 32. UCC28180 qu29_de_lusbq5.gif
Equation 33. UCC28180 qu30_de_lusbq5.gif

The duty cycle is a function of the rectified input voltage and will be continuously changing over the half line cycle. The duty cycle, DUTY(max), can be calculated at the peak of the minimum input voltage:

Equation 34. UCC28180 qu31_de_lusbq5.gif
Equation 35. UCC28180 qu32_de_lusbq5.gif
Equation 36. UCC28180 qu33_de_lusbq5.gif Boost Diode

The diode losses are estimated based upon the forward voltage drop, VF, at 125°C and the reverse recovery charge, QRR, of the diode. Using a silicon carbide Schottky diode, although more expensive, will essentially eliminate the reverse recovery losses and result in less power dissipation:

Equation 37. UCC28180 qu34_de_lusbq5.gif
Equation 38. UCC28180 qu35_de_lusbq5.gif
Equation 39. UCC28180 qu36_de_lusbq5.gif
Equation 40. UCC28180 qu37_de_lusbq5.gif

This output diode should have a blocking voltage that exceeds the output over voltage of the converter and be attached to an appropriately sized heat sink. Switching Element

The MOSFET/IGBT switch will be driven by a GATE output that is clamped at 15.2 V for VCC bias voltages greater than 15.2 V. An external gate drive resistor is recommended to limit the rise time and to dampen any ringing caused by the parasitic inductances and capacitances of the gate drive circuit; this will also help in meeting any EMI requirements of the converter. The design example uses a 3.3-Ω resistor; the final value of any design is dependent upon the parasitic elements associated with the layout of the design. To facilitate a fast turn off, a standard 40-V, 1-A Schottky diode is placed anti-parallel with the gate drive resistor. A 10-kΩ resistor is placed between the gate of the MOSFET/IGBT and ground to discharge the gate capacitance and protect from inadvertent dv/dt triggered turn-on.

The conduction losses of the switch MOSFET, in this design are estimated using the RDS(on) at 125°C, found in the device data sheet, and the calculated drain to source RMS current, IDS_RMS:

Equation 41. UCC28180 qu38_de_lusbq5.gif
Equation 42. UCC28180 qu39_de_lusbq5.gif
Equation 43. UCC28180 qu40_de_lusbq5.gif
Equation 44. UCC28180 qu41_de_lusbq5.gif
Equation 45. UCC28180 qu42_de_lusbq5.gif

The switching losses are estimated using the rise time, tr, and fall time, tf, of the MOSFET gate, and the output capacitance losses.

Equation 46. tr=5 nsUCC28180 qu43_de_lusbq5.gif
Equation 47. UCC28180 qu44_de_lusbq5.gif
Equation 48. tr=5 nsUCC28180 qu45_de_lusbq5.gif

Total FET losses

Equation 49. UCC28180 qu46_de_lusbq5.gif

The MOSFET requires an appropriately sized heat sink. Sense Resistor

To accommodate the gain of the non-linear power limit, the sense resistor, RSENSE, is sized such that it triggers the soft over current at 10% higher than the maximum peak inductor current using the minimum soft over current threshold of the ISENSE pin, VSOC, of ISENSE equal to 0.265 V.

Equation 50. UCC28180 qu47_de_lusbq5.gif
Equation 51. UCC28180 qu48_de_lusbq5.gif

The power dissipated across the sense resistor, PRSENSE, must be calculated:

Equation 52. UCC28180 qu49_de_lusbq5.gif
Equation 53. UCC28180 qu50_de_lusbq5.gif

The peak current limit, PCL, protection feature is triggered when current through the sense resistor results in the voltage across RSENSE to be equal to the VPCL threshold. For a worst case analysis, the maximum VPCL threshold is used:

Equation 54. UCC28180 qu51_de_lusbq5.gif
Equation 55. UCC28180 qu52_de_lusbq5.gif

To protect the device from inrush current, a standard 220-Ω resistor, RISENSE, is placed in series with the ISENSE pin. A 1000-pF capacitor is placed close to the device to improve noise immunity on the ISENSE pin. Output Capacitor

The output capacitor, COUT, is sized to meet holdup requirements of the converter. Assuming the downstream converters require the output of the PFC stage to never fall below 300 V, VOUT_HOLDUP(min), during one line cycle, tHOLDUP = 1/fLINE(min), the minimum calculated value for the capacitor is:

Equation 56. UCC28180 qu53_de_lusbq5.gif
Equation 57. UCC28180 qu54_de_lusbq5.gif

It is advisable to de-rate this capacitor value by 10%; the actual capacitor used is 270 µF.

Verifying that the maximum peak-to-peak output ripple voltage will be less than 5% of the output voltage ensures that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the controller. If the output ripple voltage is greater than 5% of the regulated output voltage, a larger output capacitor is required. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current of the output capacitor is calculated:

Equation 58. UCC28180 qu55_de_lusbq5.gif
Equation 59. UCC28180 qu56_de_lusbq5.gif
Equation 60. UCC28180 qu57_de_lusbq5.gif
Equation 61. UCC28180 qu58_de_lusbq5.gif

The required ripple current rating at twice the line frequency is equal to:

Equation 62. UCC28180 qu59_de_lusbq5.gif
Equation 63. UCC28180 qu60_de_lusbq5.gif

There is a high frequency ripple current through the output capacitor:

Equation 64. UCC28180 qu61_de_lusbq5.gif
Equation 65. UCC28180 qu62_de_lusbq5.gif

The total ripple current in the output capacitor is the combination of both and the output capacitor must be selected accordingly:

Equation 66. UCC28180 qu63_de_lusbq5.gif
Equation 67. UCC28180 qu64_de_lusbq5.gif Output Voltage Set Point

For low power dissipation and minimal contribution to the voltage set point, it is recommended to use 1 MΩ for the top voltage feedback divider resistor, RFB1. Multiple resistors in series are used due to the maximum allowable voltage across each. Using the internal 5-V reference, VREF, the bottom divider resistor, RFB2, is selected to meet the output voltage design goals.

Equation 68. UCC28180 qu65_de_lusbq5.gif
Equation 69. UCC28180 qu66_de_lusbq5.gif

A standard value 13-kΩ resistor for RFB2 results in a nominal output voltage set point of 391 V.

An output over voltage is detected when the output voltage exceeds its nominal set-point level by 5%, as measured when the voltage at VSENSE is 105% of the reference voltage, VREF. At this threshold, the enhanced dynamic response (EDR) is triggered and the non-linear gain to the voltage error amplifier will increase the transconductance to VCOMP and quickly return the output to its normal regulated value. This EDR threshold occurs when the output voltage reaches the VOUT(ovd) level:

Equation 70. UCC28180 qu67_de_lusbq5.gif
Equation 71. UCC28180 qu68_de_lusbq5.gif
Equation 72. UCC28180 qu69_de_lusbq5.gif

In the event of an extreme output over voltage event, the GATE output will be disabled if the output voltage exceeds its nominal set-point value by 9%. The output voltage, VOUT(ovp), at which this protection feature is triggered is calculated as follows:

Equation 73. UCC28180 qu70_de_lusbq5.gif

An output under voltage is detected when the output voltage falls below 5% below its nominal set-point as measured when the voltage at VSENSE is 95% of the reference voltage, VREF:

Equation 74. UCC28180 qu71_de_lusbq5.gif
Equation 75. UCC28180 qu72_de_lusbq5.gif
Equation 76. UCC28180 qu73_de_lusbq5.gif

A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that the RC time constant is limited to approximately 10 µs so as not to significantly reduce the control response time to output voltage deviations.

Equation 77. UCC28180 qu74_de_lusbq5.gif

The closest standard value of 820 pF was used on VSENSE for a time constant of 10.66 µs. Loop Compensation

The current loop is compensated first by determining the product of the internal loop variables, M1M2, using the internal controller constants K1 and KFQ. Compensation is optimized maximum load and nominal input voltage, 115 VAC is used for the nominal line voltage for this design:

Equation 78. UCC28180 qu75_de_lusbq5.gif
Equation 79. UCC28180 qu76_de_lusbq5.gif
Equation 80. UCC28180 qu77_de_lusbq5.gif

The VCOMP operating point is found on the following chart, M1M2 vs. VCOMP. Once the M1M2 result is calculated above, find the resultant VCOMP voltage at that operating point to calculate the individual M1 and M2 components.

UCC28180 fig2_de_lusbq5.png Figure 31. M1M2 vs. VCOMP

For the given M1M2 of 0.751 V/µs, the VCOMP approximately equal to 3 V, as shown in Figure 31.

The individual loop factors, M1 which is the current loop gain factor, and M2 which is the voltage loop PWM ramp slope, are calculated using the following conditions:

The M1 non-linear current loop gain factor follows the following identities:

Equation 81. UCC28180 qu78_de_lusbq5.gif if VCOMP < 1 V
Equation 82. UCC28180 qu79_de_lusbq5.gif if 1 V < VCOMP < 2 V
Equation 83. UCC28180 qu80_de_lusbq5.gif if 2 V < VCOMP < 4.5 V
Equation 84. UCC28180 qu81_de_lusbq5.gif if 4.5 V < VCOMP < 5 V

In this example, according to the chart in Figure 31, VCOMP is approximately equal to 3 V, so M1 is calculated to be approximately equal to 0.366:

Equation 85. UCC28180 qu82_de_lusbq5.gif

The M2 non-linear PWM ramp slope will obey the following relationships:

Equation 86. UCC28180 qu83_de_lusbq5.gif if VCOMP ≤ 0.5 V
Equation 87. UCC28180 qu84_de_lusbq5.gif if 0.5 V ≤ VCOMP ≤ 4.6 V
Equation 88. UCC28180 qu85_de_lusbq5.gif if 4.6 V ≤ VCOMP ≤ 5 V

In this example, with VCOMP approximately equal to 3 V, M2 equals 1.388 V/µs:

Equation 89. UCC28180 qu86_de_lusbq5.gif

Verify that the product of the individual gain factors, M1 and M2, is approximately equal to the M1M2 factor determined above, if not, iterate the VCOMP value and recalculate M1M2

Equation 90. UCC28180 qu87_de_lusbq5.gif

The product of M1 and M2 is within 1% of the M1M2 factor previously calculated:

Equation 91. UCC28180 qu88_de_lusbq5.gif
Equation 92. UCC28180 qu89_de_lusbq5.gif

If more accuracy was desired, iteration results in a VCOMP value of 3.004 V where M1M2 and M1 x M2 are both equal to 0.751 V/µs.

The non-linear gain variable, M3, can now be calculated:

Equation 93. UCC28180 qu90_de_lusbq5.gif if VCOMP < 5 V
Equation 94. UCC28180 qu91_de_lusbq5.gif if 0.5 V < VCOMP < 1 V
Equation 95. UCC28180 qu92_de_lusbq5.gif if 1 V < VCOMP < 2 V
Equation 96. UCC28180 qu93_de_lusbq5.gif if 2 V < VCOMP < 4.5 V
Equation 97. UCC28180 qu93_de_lusbq5.gif if 4.5 V < VCOMP < 4.6 V
Equation 98. UCC28180 qu95_de_lusbq5.gif if 4.6 V < VCOMP < 5 V

In this example, using 3.004 V for VCOMP for a more precise calculation, M3 calculates to 1.035 V/µs:

Equation 99. UCC28180 qu96_de_lusbq5.gif

For designs that allow a high inductor ripple current, the current averaging pole, which functions to flatten out the ripple current on the input of the PWM comparator, should be at least decade before the converter switching frequency. Analysis on the completed converter may be needed to determine the ideal compensation pole for the current averaging circuit as too large of a capacitor on ICOMP will add phase lag and increase iTHD where as too small of an ICOMP capacitor will result in not enough averaging and an unstable current averaging loop. The frequency of the current averaging pole, fIAVG, is chosen to be at approximately 5 kHz for this design as the current ripple factor, ∆IRIPPLE, was chosen at the onset of the design process to be 40%, which is large enough to force DCM operation and result in relatively high inductor ripple current. The required capacitor on ICOMP, CICOMP, for this is determined using the transconductance gain, gmi, of the internal current amplifier:

Equation 100. UCC28180 qu97_de_lusbq5.gif
Equation 101. UCC28180 qu98_de_slusbq5.gif

A standard value 2700-pF capacitor for CICOMP results in a current averaging pole frequency of 4.314 kHz.

Equation 102. UCC28180 qu99_de_lusbq5.gif

The transfer function of the current loop can be plotted:

Equation 103. UCC28180 qu100_de_lusbq5.gif
Equation 104. UCC28180 qu101_de_lusbq5.gif
UCC28180 fig3_de_lusbq5.png Figure 32. Bode Plot of the Current Averaging Circuit

The voltage transfer function, GVL(f) contains the product of the voltage feedback gain, GFB, and the gain from the pulse width modulator to the power stage, GPWM_PS, which includes the pulse width modulator to power stage pole, fPWM_PS. The plotted result is shown in Figure 32.

Equation 105. UCC28180 qu102_de_lusbq5.gif
Equation 106. UCC28180 qu103_de_lusbq5.gif
Equation 107. UCC28180 qu104_de_lusbq5.gif
Equation 108. UCC28180 qu105_de_lusbq5.gif
UCC28180 fig4_de_lusbq5.png Figure 33. Bode Plot of the Open Voltage Loop without Error Amplifier

The voltage error amplifier is compensated with a zero, fZERO, at the fPWM_PS pole and a pole, fPOLE, placed at 20 Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, fV, is desired to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.

Equation 109. UCC28180 qu106_de_lusbq5.gif
Equation 110. UCC28180 qu107_de_lusbq5.gif
Equation 111. UCC28180 qu108_de_lusbq5.gif

From Figure 33, the gain of the voltage transfer function at 10 Hz is approximately 0.081 dB. Estimating that the parallel capacitor, CVCOMP_P, is much smaller than the series capacitor, CVCOMP, the unity gain will be at fV, and the zero will be at fPWM_PS, the series compensation capacitor is determined:

Equation 112. UCC28180 qu109_de_lusbq5.gif
Equation 113. UCC28180 qu110_de_lusbq5.gif
Equation 114. UCC28180 qu111_de_lusbq5.gif

The capacitor for VCOMP must have a voltage rating that is greater than the absolute maximum voltage rating of the VCOMP pin, which is 7 V. The readily available standard value capacitor that is rated for at least 10 V in the package size that would fit the application was 4.7 µF and this is the value used for CVCOMP in this design example.

RVCOMP is calculated using the actual CVCOMP capacitor value.

Equation 115. UCC28180 qu112_de_lusbq5.gif
Equation 116. UCC28180 qu113_de_lusbq5.gif
Equation 117. UCC28180 qu114_de_lusbq5.gif

A 22.6-kΩ resistor is used for RVCOMP.

Equation 118. UCC28180 qu115_de_lusbq5.gif
Equation 119. UCC28180 qu115a_de_lusbq5.gif

A 0.47-µF capacitor is used for CVCOMP_P.

The total closed loop transfer function, GVL_total, contains the combined stages and is plotted in Figure 34.

Equation 120. UCC28180 qu117_de_lusbq5.gif
Equation 121. UCC28180 qu118_de_lusbq5.gif
UCC28180 fig5_de_lusbq5.png Figure 34. Closed Loop Voltage Bode Plot

9.2.3 Application Curve

UCC28180 C001_SLUUAT3.png Figure 35. UCC28180EVM-573 Efficiency
(As a Function of Line Voltage and Load Current)
UCC28180 C003_SLUUAT3.gif Figure 37. UCC28180EVM-573 Total Harmonic Distortion
(As a Function of Line Voltage and Load Current)
UCC28180 C005_SLUUAT3.png Figure 39. UCC28180EVM-573 Current Harmonics,
(115-VAC, 60-Hz Input, Full Load, Without the Fundamental)
UCC28180 C002_SLUUAT3.gif Figure 36. UCC28180EVM-573 Power Factor
(As a Function of Line Voltage and Load Current)
UCC28180 C004_SLUUAT3.png Figure 38. UCC28180EVM-573 Current Harmonics,
(230-VAC, 50-Hz Input, Full Load, Without the Fundamental)