SLUSBQ5D November   2013  – July 2016 UCC28180


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Soft Start
      2. 8.3.2  System Protection
      3. 8.3.3  VCC Undervoltage LockOut (UVLO)
      4. 8.3.4  Output Overvoltage Protection (OVP)
      5. 8.3.5  Open Loop Protection/Standby (OLP/Standby)
      6. 8.3.6  ISENSE Open-Pin Protection (ISOP)
      7. 8.3.7  ICOMP Open-Pin Protection (ICOMPP)
      8. 8.3.8  FAULT Protection
      9. 8.3.9  Output Overvoltage Detection (OVD), Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)
      10. 8.3.10 Overcurrent Protection
      11. 8.3.11 Soft Overcurrent (SOC)
      12. 8.3.12 Peak Current Limit (PCL)
      13. 8.3.13 Current Sense Resistor, RISENSE
      14. 8.3.14 ISENSE Pin
      15. 8.3.15 Gate Driver
      16. 8.3.16 Current Loop
      17. 8.3.17 ISENSE and ICOMP Functions
      18. 8.3.18 Pulse Width Modulator
      19. 8.3.19 Control Logic
      20. 8.3.20 Voltage Loop
      21. 8.3.21 Output Sensing
      22. 8.3.22 Voltage Error Amplifier
      23. 8.3.23 Non-Linear Gain Generation
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Current Calculations
        2.  Switching Frequency
        3.  Bridge Rectifier
        4.  Inductor Ripple Current
        5.  Input Capacitor
        6.  Boost Inductor
        7.  Boost Diode
        8.  Switching Element
        9.  Sense Resistor
        10. Output Capacitor
        11. Output Voltage Set Point
        12. Loop Compensation
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Bias Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support . .
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

8-Pin SOIC
D Package
UCC28180 pin_lusbq5.gif

Pin Functions

GATE 8 O Gate Drive: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 2.0-A sink and 1.5-A source capability. Output voltage is typically clamped at 15.2 V (typical).
GND 1 Ground: device ground reference.
ICOMP 2 O Current Loop Compensation: Transconductance current amplifier output. A capacitor connected to GND provides compensation and averaging of the current sense signal in the current control loop. The controller is disabled if the voltage on ICOMP is less than 0.2 V, (ICOMPP protection function).
ISENSE 3 I Inductor Current Sense: Input for the voltage across the external current sense resistor, which represents the instantaneous current through the PFC boost inductor. This voltage is averaged by the current amplifier to eliminate the effects of ripple and noise. Soft Over Current (SOC) limits the average inductor current. Cycle-by-cycle peak current limit (PCL) immediately shuts off the GATE drive if the peak-limit voltage is exceeded. An internal 2.3-µA current source pulls ISENSE above 0.085 V to shut down PFC operation if this pin becomes open-circuited, (ISOP protection function). Use a 220-Ω resistor between this pin and the current sense resistor to limit inrush-surge currents into this pin.
VCC 7 Device Supply: External bias supply input. Under-Voltage Lockout (UVLO) disables the controller until VCC exceeds a turn-on threshold of 11.5 V. Operation continues until VCC falls below the turn-off (UVLO) threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 µF minimum value should be connected from VCC to GND as close to the device as possible for high-frequency filtering of the VCC voltage.
VCOMP 5 O Voltage Loop Compensation: Transconductance voltage error amplifier output. A resistor-capacitor network connected from this pin to GND provides compensation. VCOMP is held at GND until VCC, and VSENSE exceed their threshold voltages. Once these conditions are satisfied, VCOMP is charged until the VSENSE voltage reaches its nominal regulation level. When Enhanced Dynamic Response (EDR) is engaged, a higher transconductance is applied to VCOMP to reduce the charge or discharge time for faster transient response. Soft Start is programmed by the capacitance on this pin. VCOMP is pulled low when VCC UVLO, OLP/Standby, ICOMPP and ISOP functions are activated.
FREQ 4 O Switching Frequency Setting: This pin allows the setting of the operating switching frequency by connecting a resistor to ground. The programmable frequency range is from 18 kHz to 250 kHz.
VSENSE 6 I Output Voltage Sense: An external resistor-divider network connected from this pin to the PFC output voltage provides feedback sensing for regulation to the internal 5-V reference voltage. A small capacitor from this pin to GND filters high-frequency noise. Standby disables the controller and discharges VCOMP when the voltage at VSENSE drops below the Open-Loop Protection (OLP) threshold of 16.5%VREF (0.82 V). An internal 100-nA current source pulls VSENSE to GND during pin disconnection. Enhanced Dynamic Response (EDR) rapidly returns the output voltage to its normal regulation level when a system line or load step causes VSENSE to rise above 105% or fall below 95% of the reference voltage. Two level Output Over-Voltage Protection (OVP): a 4-kΩ resistor connects VCOMP to ground to rapidly discharge VCOMP when VSENSE exceeds 107% (VOVP_L) of the reference voltage. If VSENSE exceeds 109% (VOVP_H) of the reference voltage, GATE output will be disabled until VSENSE drops below 102% of the reference voltage.