SLUSBQ5D November   2013  – July 2016 UCC28180


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Soft Start
      2. 8.3.2  System Protection
      3. 8.3.3  VCC Undervoltage LockOut (UVLO)
      4. 8.3.4  Output Overvoltage Protection (OVP)
      5. 8.3.5  Open Loop Protection/Standby (OLP/Standby)
      6. 8.3.6  ISENSE Open-Pin Protection (ISOP)
      7. 8.3.7  ICOMP Open-Pin Protection (ICOMPP)
      8. 8.3.8  FAULT Protection
      9. 8.3.9  Output Overvoltage Detection (OVD), Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)
      10. 8.3.10 Overcurrent Protection
      11. 8.3.11 Soft Overcurrent (SOC)
      12. 8.3.12 Peak Current Limit (PCL)
      13. 8.3.13 Current Sense Resistor, RISENSE
      14. 8.3.14 ISENSE Pin
      15. 8.3.15 Gate Driver
      16. 8.3.16 Current Loop
      17. 8.3.17 ISENSE and ICOMP Functions
      18. 8.3.18 Pulse Width Modulator
      19. 8.3.19 Control Logic
      20. 8.3.20 Voltage Loop
      21. 8.3.21 Output Sensing
      22. 8.3.22 Voltage Error Amplifier
      23. 8.3.23 Non-Linear Gain Generation
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Current Calculations
        2.  Switching Frequency
        3.  Bridge Rectifier
        4.  Inductor Ripple Current
        5.  Input Capacitor
        6.  Boost Inductor
        7.  Boost Diode
        8.  Switching Element
        9.  Sense Resistor
        10. Output Capacitor
        11. Output Voltage Set Point
        12. Loop Compensation
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Bias Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support . .
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. Separating the high di/dt induced noise on the power ground from the low current quiet signal ground is required for adequate noise immunity. Even with a signal layer PCB design, the pin out of the UCC28180 is ideally suited to minimize noise on the small signal traces. As shown in Figure 41, the capacitors on VSENSE, VCOMP, ISENSE, ICOMP, and FREQ (if used) must be all be returned directly to the portion of the ground plane that is the quiet signal GND and not in high-current return path of the converter, shown as power GND. The trace from the FREQ pin to the frequency programming resistor should be as short as possible. It is recommended that the compensation components on ICOMP and VCOMP are located as close as possible to the UCC28180. Placement of these components should take precedence, paying close attention to keeping their traces away from high noise areas. The bypass capacitors on VCC must be located physically close the VCC and GND pins of the UCC28180 but should not be in the immediate path of the signal return.

Other layout considerations should include keeping the switch node as short as possible, with a wide trace to reduce induced ringing caused by parasitic inductance. Every effort should be made to avoid noise from the switch node from corrupting the small signal traces with adequate clearance and ground shielding. As some compromises must be made due to limitation of PCB layers or space constraints, traces that must be made long, such as the signal from the current sense resistor shown in Figure 41, should be as wide as possible, avoid long narrow traces.

Table 2. Layout Component Description for Figure 41

U1 Controller, UCC28180
Q1 Main switch
D2 Boost diode
R7 Pull-down resistor on GATE
D1 Turn-off diode on GATE
D4 ISENSE pin diode
C11, C12 VCC bypass capacitors
C7 ICOMP compensation, CICOMP
R1, C6 Placeholders for additional ICOMP compensation, if needed
R2 ISENSE inrush current limiting resistor, RISENSE
R3 Frequency programming resistor, RFREQ
C9 Placeholder for FREQ filter, if needed
R6, C13, C14 VCOMP compensation components, RVCOMP, CVCOMP_P, CVCOMP
R11, R12 RFB1 on VSENSE

11.2 Layout Example

UCC28180 layout_slusbq5.gif Figure 41. Recommended Layout for UCC28180