The controller applies a line-dependent reduction in the peak-current demand to correct for the current overshoot due to the PWM and gate drive propagation delay, with the aim of delivering a constant peak current versus line at a given power level. This maintains approximately constant switching frequency versus line for a given power level (until the operation enters into CCM), improves regulation, reduces audio noise, and allows lower standby power at high line. If not corrected, the current overshoot could become significant at high line, where the inductor current di/dt is higher. This overshoot would cause a pronounced increase in transferred power per switching cycle at high line, because power is proportional to IPK2. The effect of the delay on the peak-current overshoot is illustrated in Figure 32.
For different power stage designs, the combination of primary magnetizing inductance LPRI, current sense resistance RCS and external MOSFET gate turn-off delay tOFF(ext), must be verified against Equation 17, to ensure that the internal peak-current compensation gain range is satisfied. The KLINE(adj) factor should be within the range indicated. If the external turn-off delay is too long, then the internal IPEAK adjustment factor is too low, and the adjustment at high line is not able to achieve the required level of over-shoot compensation. As noted previously, this could result in regulation difficulties at no-load, and may cause poor line and load regulation, or require an increase in output pre-load power.