Size the VDD capacitor to supply sufficient IDD(run) current to the device during initial start-up, and also during the charging phase of the main output capacitors. During the charging phase the bias winding on the transformer must supply the bias power. When VDD reaches the VDD(start) threshold, the device consumes IDD(run) for tSTART(del) before the PWM switching commences. Thereafter, the bias current is the device current plus the MOSFET gate current. The VDD capacitor must support this higher level of current until the output is sufficiently charged that the bias winding rail has increased above the VDD(stop) level.
Calculate the required bias capacitance from the total bias charge associated with the device run current during the tSTART(del) phase, plus the device run current during the output charge phase, plus the primary MOSFET gate charge current during the output charge phase. The time taken for the output charge phase to reach a sufficient level to supply the bias can be calculated from the size of the output capacitor, target output regulation voltage, and the difference between the available CC mode current limit and the maximum load current (assuming that the output capacitor has to be charged whilst also supplying full rated load current). Assume that the MOSFET is switched at 60 kHz throughout the charging phase.
Combining these into one equation, the required VDD capacitor can be calculated as shown in Equation 57.
This can be re-written with the explicit device values substituted:
For this EVM design, the MOSFET Qg(tot) is 30 nC, VBIAS(nom) is 12.6 V. IO(max) is 3.35 A, so this equates to:
Choose the next higher standard value, 22 μF.