SLUSC18A September   2014  – March 2015 UCC29950


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1. 5.1 Detailed Pin Descriptions
      1. 5.1.1  VCC
      2. 5.1.2  MD_SEL/PS_ON
      3. 5.1.3  SUFG, SUFS
      4. 5.1.4  GD1, GD2
      5. 5.1.5  GND
      6. 5.1.6  AGND
      7. 5.1.7  LLC_CS
      8. 5.1.8  FB
      9. 5.1.9  PFC_GD
      10. 5.1.10 PFC_CS
      11. 5.1.11 VBULK
      12. 5.1.12 AC1, AC2
      13. 5.1.13 AC_DET
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Storage Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Sense Networks
      2. 7.3.2  Sense Network Fault Detection
      3. 7.3.3  PFC Stage Soft-Start
      4. 7.3.4  AC Line Voltage Sensing
      5. 7.3.5  VBLK Sensing
      6. 7.3.6  AC Input UVLO and Brownout Protection
      7. 7.3.7  Dither
      8. 7.3.8  Active X-Cap Discharge
      9. 7.3.9  LLC Stage Soft Start
      10. 7.3.10 PFC Stage Current Sensing
      11. 7.3.11 Input Power Limit
      12. 7.3.12 PFC Stage Soft Start
      13. 7.3.13 Hybrid PFC Control Loop
      14. 7.3.14 PFC Stage Second Current Limit
      15. 7.3.15 PFC Inductor and Bulk Capacitor Recommendations
      16. 7.3.16 PFC Stage Over Voltage Protection
      17. 7.3.17 LLC Stage Control
      18. 7.3.18 Driver Output Stages and Characteristic
      19. 7.3.19 LLC Stage Dead Time Profile
      20. 7.3.20 LLC Stage Current Sensing
      21. 7.3.21 LLC Three Level Over-Current Protection
      22. 7.3.22 Over-Temperature Protection
      23. 7.3.23 Fault Timer and Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Selection
      2. 7.4.2 Start-Up in Aux Bias Mode
      3. 7.4.3 Start-Up Operation in Self-Bias Mode
      4. 7.4.4 Bias Rail UVLO
      5. 7.4.5 LLC Stage MOSFET Drive
      6. 7.4.6 Gate Drive Transformer
      7. 7.4.7 Gate Drive Device
      8. 7.4.8 Comparison
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  LLC Stage
        2.  LLC Switching Frequency
        3.  LLC Transformer Turns Ratio
        4.  LLC Stage Equivalent Load Resistance
        5.  LLC Gain Range
        6.  Select LN and QE
        7.  LLC No-Load Gain
        8.  Parameters of the LLC Resonant Circuit
        9.  Verify the LLC Resonant Circuit Design
        10. LLC Primary-Side Currents
        11. LLC Secondary-Side Currents
        12. LLC Transformer
        13. LLC Resonant Inductor
        14. Combining the LLC Resonant Inductor and Transformer
        15. LLC Resonant Capacitor
        16. LLC Stage with Split Resonant Capacitor
        17. LLC Primary-Side MOSFETs
        18. LLC Output Rectifier Diodes
        19. LLC Stage Output Capacitors
        20. LLC Stage Over-Current Protection, Current Sense Resistor
        21. Detailed Design Procedure for the PFC stage
        22. PFC Stage Output Current Calculation
        23. Line Current Calculation
        24. Bridge Rectifier
        25. PFC Boost Inductor
        26. PFC Input Capacitor
        27. PFC Stage MOSFET
        28. PFC Boost Diode
        29. Bulk Capacitor
        30. PFC Stage Current Sense Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  GND Pin
      2. 10.1.2  GD1, GD2 Pins
      3. 10.1.3  VCC Pin
      4. 10.1.4  SUFG Pin
      5. 10.1.5  SUFS Pin
      6. 10.1.6  AGND Pin
      7. 10.1.7  MD_SEL/PS_ON Pin
      8. 10.1.8  VBULK Pin
      9. 10.1.9  AC1, AC2 Pins
      10. 10.1.10 LLC_CS
      11. 10.1.11 FB
      12. 10.1.12 PFC_CS
      13. 10.1.13 AC_DET
      14. 10.1.14 PFC_GD
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The UCC29950 combines all the functions necessary to control a Boost PFC and LLC power system. It is packaged in an SOIC-16 package. The SUFG and SUFS pins allow the system designer to use an external depletion mode MOSFET to provide start up power instead of using a dissipative resistor. The use of high-impedance voltage sensing networks further reduces standby power. The combo device uses information from both PFC and LLC stages to optimize the system efficiency, transient response and standby power. The controller can be operated with bias current supplied from a small external PSU (Aux Bias) or from a winding on the LLC transformer (Self Bias). In Aux Bias Mode, the MD_SEL/PS_ON pin allows the user to turn on the PFC stage alone or both PFC and LLC stages.

The UCC29950 has many protection features, these include:

  • Bias Rail Under-Voltage Lockout
  • Active X-Cap Discharge
  • Line Under-Voltage Detection
  • Line Over-Voltage Detection
  • Line Brownout Detection
  • Three Level Output Overcurrent Profile on LLC Stage
  • PFC Stage Constant Input Power Limit
  • PFC Stage Input Current Limit
  • PFC Stage Second Current Limit
  • PFC Stage Output Overvoltage Protection
  • VBLK Sensing Network Fault Detection
  • VBLK Over-Voltage Protection
  • PFC and LLC Stage Soft-Start
  • PFC Stage Frequency Dithering
  • Thermal Shutdown

The UCC29950 implements an advanced control algorithm to control the PFC stage input current. This proprietary hybrid method combines both average and peak-mode control methods.

  • Accurate control of the average current drawn from the line gives good THD.
  • Peak inductor current information is used to terminate each PFC switching cycle.
  • The algorithm is insensitive to variations in the peak-to-average current ratio.

The input current is accurately controlled so that it follows the correct sinusoidal shape and also gives inherent cycle-by-cycle protection against excess MOSFET current. A further advantage is that the control loop is insensitive to PFC inductor and bulk capacitor variations. The UCC29950 takes full advantage of this fact to implement internal compensation of the PFC stage. This simplifies the system designer’s task and reduces the external component count. A sophisticated soft-start algorithm is used to achieve a constant soft-start ramp time over a wide range of bulk capacitor values and initial conditions.

An LLC stage is typically used to convert the PFC stage output to an isolated final voltage for system use. The UCC29950 provides all the primary-side functions needed to control such a second stage. The input to the FB pin is an isolated control signal from the output. This signal is fed into a voltage-to-frequency converter (VCO). The VCO inserts an appropriate dead time and the resulting signals are routed through some on-chip drivers connected to the GD1 and GD2 outputs. The dead time is shortest at low LLC frequencies and is increased automatically as frequency is increased. A three level Over-Current Protection (OCP) function stops the GD1 and GD2 signals if the current signal at the LLC_CS pin goes outside of a defined current vs time profile.

7.2 Functional Block Diagram

UCC29950 block_lusc18.gif

7.3 Feature Description

Table 1. UCC29950 Features and Benefits

Feature Benefit
Self-Bias Mode allowing off-line operation Eliminate cost of Auxiliary Flyback Bias supply in system
Control output for external high-voltage, depletion mode start-up MOSFET Eliminates drop resistor from rectified AC line, reduces stand-by power
Integrated X-Cap discharge function using external start-up MOSFET Eliminates bleed resistor across differential EMI filter capacitor, reduces stand-by power
PFC stage design in 3 easy steps - (i) design voltage feedback network, (ii) choose current sense feedback resistor, (iii) design power stage Greatly simplifies design effort
Advanced control algorithm for PFC Stage Good iTHD and insensitivity to inductor and bulk capacitor variations, Cycle by cycle PFC overcurrent protection
Internal compensation of PFC Stage Voltage and Current feedback loops Reduces Component count, eliminates 2 design steps (voltage and current loop compensation)
Differential AC Line sensing with fixed 9.3M-ohm resistors Accurate measurement of line conditions under no-load or start-up conditions for improved performance and protection - Eliminates 1 design step (AC line sensing)
PFC frequency dithering Simplifies EMI filtering and eases EMI compliance
True input power limit, independent of line voltage Limit set by choice of RCS(pfc) allowing designer greater flexibility compared to fixed limits that depending on AC line voltage
Zero Voltage Switching (ZVS) over a wide range of operating conditions Reduced switching losses in the LLC converter power devices
Three Level over current protection for LLC and Hiccup mode of operation Allows the power stage to ride through a short-term transient overload but reacts quickly to protect the power stage from heavy overload or output short-circuit events.

7.3.1 Sense Networks

The UCC29950 uses fixed scaling factors to measure the signals at its pins. The circuit position of the voltage sensing resistors is shown in Figure 9. The current sensing resistors are shown in Figure 13.

The resistors in the VBLK sensing network, RTOP and RBOT in Figure 9 have been chosen to minimize the power dissipation and ensure correct operation over the expected tolerance bands. The impedance in this network may be reduced by choosing lower value resistors provided that the potential division ratio is unchanged or kept within the limits given below.

The nominal ratio is 30 MΩ/73.33 kΩ = 409.28. This has been chosen to give a nominal VBULK regulation setpoint of 385 V. This voltage is the ideal operating point for the PFC. It prevents direct conduction into the bulk capacitor at high line and prevents false OVP tripping due to load transients - especially under high load conditions where the voltage ripple on the bulk capacitor is maximum. It is possible to change the nominal setpoint within the limits below.

If the ratio is increased above the nominal value then there is a risk of triggering a sense network fault condition at startup - as described in the next section. The maximum ratio is not an absolutely fixed value but is likely to be about 425 with a corresponding VBULK regulation setpoint of 400 V. The minimum ratio is governed by the desire to avoid direct conduction into the bulk capacitor when operating at high line. VBULK must be greater than 374 V to avoid this condition on a 264 VRMS line. The corresponding minimum ratio is about 395.

Table 2. Sensing Resistor Values

RL1 and RL2 1% tolerance parts are recommended. To meet voltage ratings, it may be necessary to split the resistance across more than one part. 9.21 9.30 9.40
RTOP 1% tolerance parts are recommended. To meet voltage ratings, it may be necessary to split the resistance across more than one part. 29.7 30.0 30.3
RBOT 1% tolerance parts are recommended. A parallel combination of a 75-kΩ and a 3.3-MΩ resistor gives a nominal 73.33 kΩ 72.50 73.33 74.07
RCS(pfc) Value depends on system power level and is given by Equation 59 33
RCS(llc) Value depends on system power level and is given by Equation 36 400
UCC29950 volt_sense_lusc18.gifFigure 9. Voltage Sensing Network

7.3.2 Sense Network Fault Detection

In a boost converter, there is a direct conduction path from AC line to the bulk capacitor which ensures that it will be charged to peak of line even if the PFC stage controller is inactive. At start-up the UCC29950 measures AC line voltage and the voltage on the PFC bulk energy storage capacitor. If the UCC29950 measures VBLK to be lower than VAC it enters a latched fault condition. This feature prevents the PFC stage from running if the upper resistor in the voltage sensing network has gone open circuit. If the lower resistor has gone open circuit, then the UCC29950 detects this as an over-voltage event on the output and PFC switching will not start.

7.3.3 PFC Stage Soft-Start

The UCC29950 soft-start will typically charge the PFC boost capacitor within 50 ms to 100 ms of starting.

7.3.4 AC Line Voltage Sensing

The UCC29950 uses differential AC line sensing through its AC1 and AC2 pins. Differential sensing provides more accurate measurements than single ended sensing, especially at startup and under light load conditions. It also allows faster detection of AC line disconnection or failure.

Normal single ended sensing assumes that the diodes connected to the negative going AC line are forward biased and that a single measurement of the positive going AC line is a true representation of the input voltage. This is normally true but if there is no current being drawn, as is the case under no-load or start up conditions, then it is possible that all the diodes in the bridge are reverse biased. If this happens then a single ended measurement will overestimate the true AC line voltage. The differential AC line sensing used in the UCC29950 avoids these errors.

The external resistor value impedance for AC1 and AC2 is required to be 9.3 MΩ. This reduces the static power dissipation and provides the correct divider ratio in conjunction with the GAIN and OFFSET factors of the device, (see Equation 1).

These factors are set at the time the UCC29950 is tested. They are used to compensate for device to device variations in RAC1 and RAC2.

Equation 1. UCC29950 qu1_lusc18.gif

AC1 and AC2 must be connected to the AC line side of the bridge rectifier through 9.3-MΩ resistors. The high impedance sensing network is effectively a current source which is why the levels in the electrical characteristics table are given in terms of currents rather than voltages. The equivalent voltages are given in Table 3.

The 9.3-MΩ resistors must be able to support the full voltage at peak of AC line and are conveniently made from three 3.09-MΩ resistors in series. It is recommended to minimize the length of track between the ACx pins and the lowest resistor in the chain.

Table 3. PFC AC Line Voltage Action Levels(1)

VAC(det) AC_DET will be active HIGH when VAC is below this level IAC(det) 65.5 70 74.5 VRMS
VAC(low_falling) PFC stage stops 100 ms after VAC is at or below this level IAC(low_falling) 65.5 70 74.5
VAC(low_rising) PFC stage is allowed to start when VAC is at or above this level IAC(low_rising) 75 80 85.2
VAC(high_falling) PFC stage restarts if VAC falls below this level IAC(high_falling) 287 300 313
VAC(high_rising) PFC stage stops if VAC is at or above this level IAC(high_rising) 297 310 323
VAC(halt) PFC and LLC stages stop if VAC is at or above this level IAC(halt) 306 320 333
(1) Based on parameter values in Electrical Characteristics table and calculated assuming 9.3 MΩ resistors in AC1 and AC2 lines. The relative levels of these action levels track each other.

7.3.5 VBLK Sensing

VBLK is sensed through a potential divider with a resistance of 30 MΩ between the VBULK pin and VBLK. The bottom resistor in the potential divider is 73.3 kΩ. The 30 MΩ resistor has to support the full VBLK voltage and it is normal to split this resistance into three separate parts of 10 MΩ each. As noted in Sense Network Fault Detection the UCC29950 will not start the power stages if it detects that VBLK is less than peak of VAC. Because of the high impedance nature of the sensing network it is recommended to minimize the length of track between the VBULK pin and the lowest resistor in the sensing chain.

7.3.6 AC Input UVLO and Brownout Protection

The UCC29950 provides full brownout protection and will not react to single-cycle AC line dropouts. While the PFC stage is running the controller checks each AC line half-cycle. A valid AC line input is detected if the peak voltage during an AC line half-cycle is greater than the brownout level (equivalent to 70 VRMS). The AC_DET output goes high if no valid AC line input is detected for a period greater than 32 ms and both the PFC and LLC stages stop operating 100 ms later.


The LLC stage always stops immediately if VBULK falls below VBULK(llc_stop).

UCC29950 ac_drop_lusc18.gifFigure 10. AC Line Dropout
UCC29950 ac_brown_lusc18.gifFigure 11. AC Line Disconnect
UCC29950 ac_dis_lusc18.gifFigure 12. AC Line Brownout

7.3.7 Dither

The PFC stage switching frequency is stepped between three discrete frequencies at a rate of 333 Hz. The frequencies are spaced at nominal 2-kHz intervals. The dither rate is selected to avoid harmonics of the major AC line frequencies. Dither is effective in reducing the average EMI level and also reduces the quasi-peak levels but to a lesser extent.

7.3.8 Active X-Cap Discharge

If the Active X-Cap discharge function is to be used, the drain of the start-up FET must be connected to the AC side of the bridge rectifier, as shown in Figure 20. The X-Cap is discharged by bringing SUFG low to turn the start-up FET on. The discharge path is then through the startup FET, via the SUFS pin and into CVCC.


A Zener diode should be used to clamp VCC and prevent multiple X-Cap discharge events from over charging the capacitor. This Zener diode should be 18V rated device in Self-bias applications. A lower voltage Zener could be used in Aux bias applications, providing that the Zener voltage is greater than the normal operating VCC rail voltage.

When the AC line is removed the UCC29950 detects that the zero voltage crossings on VAC have ceased. If the PFC stage is running at that time then the X-Cap is discharged through the switching action of the PFC stage and no further action is needed. If the PFC stage is not running at the time of disconnection, perhaps because MD_SEL/PS_ON is held low or VBULK is > VBULK(reg) , then SUFG is set high if VCX-Cap (the voltage on the X-Cap) is greater than 42 V and the X-Cap is discharged. If VCX-Cap is < 42 V then it is regarded as being at a safe level, discharge is not needed and SUFG is not set high. The X-Cap is always discharged within the 1 s allowed by the safety standards but there may be up to 300 ms delay or latency in SUFG operation if the controller is operating in burst mode, for example at light loads. The UCC29950 makes the decision to set SUFG high based on the voltage on the X-Cap at the end of this latency period.

7.3.9 LLC Stage Soft Start

The LLC stage soft-start ramps the LLC gate drive frequency from min period (1/LLCF(max) ) to max period (1/LLCF(min) ) over a 100-ms interval. The ramp is terminated when the voltage at the FB pin is such that it would command a higher frequency than the ramp. The first pulse from the GD1 output is half width.

7.3.10 PFC Stage Current Sensing

The UCC29950 controls the average current in the PFC inductor. This means that the current sense signal at the PFC_CS pin must represent the inductor current during the full PFC switching cycle. That is when the MOSFET is ON and also when the MOSFET is OFF. This is achieved by putting the current sensing resistor, RCS(pfc), in the position shown in Figure 13 and Figure 34.


The current sense signal, VCS_PFC, is negative going, so the signal goes more negative as the inductor current increases.

The current sensing resistor is on the input current return path and inrush currents flow through it. These may generate large voltage drops on the current sense resistor. These voltages may be higher than the negative voltage rating on the PFC_CS pin. A resistor, recommended value = 1 kΩ, between the current sensing resistor and the PFC_CS pin is used to avoid over stressing the device. Signal diodes may be necessary to provide additional clamping. A small filter capacitor may be useful to further reduce the noise level at this pin but be careful that this part does not significantly attenuate the ripple component of the current sense signal. These components are shown in Figure 13.

The current drawn from the AC line is limited so that the peak voltage on the PFC_CS pin, ignoring PFC stage switching ripple, does not exceed –225 mV, VTH(PFCCS(cav_max)), as shown in Figure 6.

There is a second current limit point at VPFCCS(max) and the peak voltage at the PFC_CS pin should not be allowed to exceed this limit (–570 mV). The operation of this second current limit is explained later. The PFC current sense resistor (RCS(pfc)) value needed can be calculated using Equation 59.

UCC29950 current_sense2_lusc18.gifFigure 13. Current Sensing Connections

7.3.11 Input Power Limit

The UCC29950 has a true input power limit which limits the PFC stage power at a level which is independent of the AC line voltage. This is more useful than a simple fixed input current limit where the power would be limited at different levels depending on the AC line voltage. The power limit is set by the choice of RCS(pfc) according to Equation 59.

7.3.12 PFC Stage Soft Start

When the power system is first connected, the bulk capacitor charges to the peak value of the AC line voltage. The PFC stage soft-start process first calculates the current needed to charge the bulk capacitor from this initial stage to the regulation setpoint (VBULK at VBULK(reg)) in a nominal 50 ms. This is an approximate calculation based on a bulk capacitance of 0.8-µF per watt and varies if a larger or smaller capacitor is used. The PFC stage is then started using this current limit value.

7.3.13 Hybrid PFC Control Loop

The UCC29950 controls a continuous-conduction mode PFC stage by using a novel method combining average current-mode control with peak-current sensing. Among other advantages, this method eliminates the peak-mode line current distortions due to a varying peak-to-average current ratio. The average current is used to control the average value of the PFC inductor current and the peak current is used to terminate each PWM cycle and provide high bandwidth, cycle-by-cycle current control or limiting. Good power factor is achieved by forcing the average input current to follow a demand signal that is derived from the AC line voltage.

Traditional current-mode control systems require resistor and capacitor compensation components to shape the system response. It is difficult to integrate these components into a semiconductor chip and external parts must be used. The UCC29950 avoids the need for external compensation networks by implementing the average portion of the control loop digitally. The entire outer-voltage control loop is digital and the required slow response is easily achieved without the need for external parts. This mixed signal approach uses digital methods for low-frequency compensation and analog op-amps and comparators for the actual PWM duty-cycle generation.

The input AC line voltage is sensed differentially through the AC1 and AC2 pins, as shown in Figure 14. Differential sensing allows more accurate measurement of the AC line voltage over the entire input power range, including no load, than single ended sensing. The output of the voltage loop is multiplied by the instantaneous line voltage, |VAC1 - VAC2|, to give an average current demand signal, IAV(dem), for the current loop. The IAV(dem), the voltage loop and |VAC1 - VAC2| signals are all implemented digitally. The voltage loop provides correct compensation over the expected range of bulk capacitor values, based on a capacitance to power ratio between 0.5 μF W-1 and 2.4 μF W-1. This eliminates the need for external compensation components and simplifies the design task.

The current-demand signal normally has a rectified sinusoidal shape. The current-loop output is used to program a duty cycle which is then sent to the PFC_GD pin through a driver. The minimum duty cycle is 0% at which point the PFG_GD output is kept low for the entire switching cycle. The maximum duty cycle for the PFC_GD output is at least 92%.


The maximum duty cycle is imposed by the PWM block independently of the input from the current loop and does not depend on inputs from the current loop or elsewhere.

UCC29950 pfc_loop_lusc18.gifFigure 14. PFC Control Loop

The inner current loop uses a hybrid mixed signal control method as shown in Figure 15. The IAV(dem) signal (digital average current demand) is converted to an analog form and summed with the sensed current signal ICS by the unity gain inverting amplifier, A1. The current sensed is the total inductor current which means that the sensing resistor must be placed in the negative return as shown in Figure 13. The IAV(dem) signal is positive going, greater IAV(dem) values commands larger currents. The signal at the PFC_CS pin is negative going so that larger currents give a more negative signal level. The action of the control loop is to keep the inverting and non-inverting inputs to A1 at the same level (450 mV). The output of the A1 amplifier contains both average and peak-inductor current information. The average level at the A1 amplifier output is extracted by the ADC and digital filter shown in the block called A2 in Figure 15. This average level is then subtracted from the fixed PWM ramp coming from the waveform generator. The result is converted into an analog signal by the DAC and sent to the inverting input of the fast analog PWM Comparator. The comparator ramp has an offset which is a function of the digital-filter output. This offset value moves up and down in response to changes at the A1 output. The comparator ramp at the inverting input is negative going and that at the non-inverting input is positive going. This increases the noise immunity of the comparator making an incorrect, early termination of the cycle is less likely.

If the IAV(dem) signal increases, for example in response to an AC line voltage or load change then the average output of the A1 amplifier initially decreases by the same amount. The PWM duty cycle, and inductor current, will then increase because as VA1(out) moves negative, it takes longer for the two signals at the comparator inputs to intersect and terminate the cycle. The digital-filter output also increases in response to the change in VA1(out) according to its frequency response characteristic and the average value of the comparator ramp moves negative. This tends to reduce the PWM duty cycle. Eventually, as the PFC inductor current increases the VA1(out) signal returns to its equilibrium point at 450 mV. The digital filter dynamically adjusts its output up or down so as to keep the average value of the comparator ramp at the level where VA1(out) is kept at 450 mV. The overall effect is that a unipolar sinusoidal demand signal is translated into a unipolar sinusoidal PFC inductor current.

UCC29950 hybrid_lusc18.gifFigure 15. UCC29950 Hybrid Current-Mode Control

7.3.14 PFC Stage Second Current Limit

An individual PFC switching cycle is normally terminated by the PWM Comparator. If for some reason the PWM Comparator fails or has stopped operating then there is a second comparator monitoring the output of the A1 amplifier (OCP Comparator in Figure 15). The OCP comparator turns the PFC MOSFET off and provides an additional protection function for the devices in the power train.

If the output of A1 reaches 850 mV then the OCP comparator trips. Two actions follow:

  1. The existing PWM cycle is terminated immediately.
  2. Both the PFC and LLC stages shut down for 1 s followed by a re-start.

7.3.15 PFC Inductor and Bulk Capacitor Recommendations

The CCM Boost converter current-mode control loop is insensitive to PFC inductor value and can operate over a wide range of inductance values. The inductor value in a given application is a trade off between ripple current, physical size, losses, cost and several other parameters. For example, in Detailed Design Procedure for the PFC stage a value of 600 µH for a 300-W application is chosen.

The hybrid control loop has been designed to be stable for any bulk capacitance between 0.5 µF W-1 and 2.4 µF W-1. For a 300-W application, this would allow the use of a bulk capacitance between 150 µF and 720 µF. These limits on PFC inductance and bulk capacitance are conservative.

7.3.16 PFC Stage Over Voltage Protection

In normal operation the PFC stage control loop in the UCC29950 regulates the PFC stage output voltage (VBLK) such that the voltage at the VBULK pin is held at VBULK(reg). If the recommended sensing network is used then this corresponds to 385 V on the bulk capacitor. If the voltage at the VBULK pin exceeds VBULK(ovp) the PFC stage is stopped immediately. It restarts once VBULK falls back to the VBULK(reg) level. The OVP level corresponds to 450 V at the PFC bulk capacitor. This protects the PFC stage against over stresses due to rapid increases in VBLK, occurring if an AC line surge event were to happen. The LLC stage continues to operate in order to load and discharge the bulk capacitor. The OVP response is immediate, of the order of 100 µs, and is more rapid than the response of the normal PFC voltage control loop.

UCC29950 vbulk_lusc18.gifFigure 16. VBULK Over-Voltage Protection

7.3.17 LLC Stage Control

The UCC29950 has three pins dedicated to the control of an LLC power stage, the two gate drives GD1 and GD2, and the feedback pin, FB. If the controller is operating in Aux Bias Mode then the MD_SEL/PS_ON pin may also be used to turn the LLC stage on or off. The UCC29950 includes an on chip Voltage to Frequency Converter (VCO) which converts the voltage on the FB pin into a square wave at the desired frequency according to the graph in Figure 1. The basic response time of the voltage to frequency conversion process is typically less than 40 µs. This means that the overall response of the LLC power system is dominated by the other components in the loop, for example, the opto-coupler and error amplifier on the output , rather than by the UCC29950. Inverted and non-inverted versions of the square wave are produced and a dead time is added. The dead time added is a function of the frequency being generated according to the graph in Figure 2. The signal is then passed to the on-chip drivers connected at the GD1 and GD2 pins. The duty cycles of the GD1 and GD2 signals are highly symmetrical, typically they match to better than 0.1%.

The first and last LLC gate drive pulses are normally half width and appear on GD1 and GD2 respectively. The half width pulses reduce any DC flux in the transformer at start up or shutdown. If the LLC_OCP3 level is exceeded then the final pulse is of normal width.

UCC29950 llc_lusc18.gifFigure 17. LLC GD1 and GD2 Start and Stop

7.3.18 Driver Output Stages and Characteristic

The output stage pull-up features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function of the N-Channel MOSFET is to provide an increased sourcing current enabling fast turn-on, as it delivers the highest peak-source current during the Miller plateau region of the power-switch turn-on transition, when the power switch drain or collector voltage experiences high dV/dt. The N-Channel device can pull the driver output to within one threshold voltage drop of the V+ rail. The P-Channel device can pull the driver output all the way to V+.

The effective resistance of the UCC29950 pull-up stage during the turn-on instant is therefore lowest during the time when the highest current is needed. The pull-down structure in UCC29950 is composed of an N-Channel MOSFET which can pull the output all the way to GND.

The structure in Figure 18 is used in the output circuit of the low power driver used to output the AC_DET signal. It has the same pull up characteristics, but at an impedance level more suitable for driving a signal level load such as an optocoupler LED.

UCC29950 drive_output_lusc18.gifFigure 18. Driver Output Stage (simplified)

7.3.19 LLC Stage Dead Time Profile

The UCC29950 programs a dead time into the LLC gate drive outputs (GD1 and GD2) which follows the profile shown in Figure 2. The dead time is longest at high frequencies because the currents in the resonant tank circuit are less and so the stray capacitances at the switched node take longer to swing from one rail to the other. At low frequencies the opposite is true, the currents in the resonant tank are greater and the switched node swings more quickly.

7.3.20 LLC Stage Current Sensing

The UCC29950 uses primary-side current sensing to monitor the output current. This has the advantage that current limiting can be implemented without having to bring a current limit signal across the primary-to-secondary isolation barrier. Also, assuming that the output voltage of the LLC stage is lower than the input, the currents in the primary circuit are lower than those in the secondary. This allows a larger value of sensing resistor to be used without incurring excessive power dissipation. One side effect of sensing on the transformer primary is that the sensed current includes start up charging currents onto the LLC stage output capacitance. The three level OCP feature allows this charging current to flow without tripping a fault. Even if the current sensing were done on the secondary side and outboard of the LLC stage output capacitance there may still be additional, off-board capacitance whose charging current does flow in the sensing resistor.

7.3.21 LLC Three Level Over-Current Protection

The UCC29950 uses the LLC stage input current to represent the output current. The value of the LLC current sense resistor that should be used is given by Equation 36.

Three levels of overcurrent protection as shown in Figure 19, are provided to allow the UCC29950 to react in a flexible manner to an over current event. VCS(ocp1) and VCS(ocp2) faults are triggered after a short delay. VCS(ocp3) level faults are acted on immediately.

Table 4. LLC Stage Over-Current Protection Levels

VCS(ocp1) First overload detection level. If this threshold is exceeded for tOCP1 then both the PFC and LLC stages will shut-down. Restart with a normal soft-start sequence after tLONG(fault) (1 s typ). 133% of VCS(llc_max). Typically 400 mV
tOCP1 52 ms
VCS(ocp2) Second overload detection level. If this threshold is exceeded for tOCP2 then both the PFC and LLC stages will shut-down. Restart with a normal soft start sequence after tLONG(fault) (1 s typ). 200% of VCS(llc_max). Typically 600 mV
tOCP2 10 ms
VCS(ocp3) Third overload detection level. If this threshold is exceeded for tOCP3 then both the PFC and LLC stages will shut-down. Restart with a normal soft start sequence after tLONG(fault) (1 s typ). 300% of VCS(llc_max). Typically 900 mV
tOCP3 This is the time the UCC29950 takes to react to a level three overload voltage at the LLC_CS pin. Board level filtering can reduce the signal rise time at the pin and significantly increase the overall reaction time. <5 µs

If any of these over-current protection events occurs the controller enters a hiccup mode of operation and it tries to restart the power stages at 1-s intervals. This graduated response allows the power stage to ride through a short-term transient overload but reacts quickly to protect the power stage from heavy overload or output short-circuit events.

UCC29950 output_protection_lusc18.gifFigure 19. UCC29950 Output Over-Current Protection Profile

7.3.22 Over-Temperature Protection

If the UCC29950 junction reaches its TSD (Thermal Shutdown Temperature) it stops both the PFC and LLC stages. The device then cools down to its TST (Start / Restart Temperature). It then initiates a full soft start of both stages, provided that the other conditions for start up are met. An over-temperature protection event is treated as a long fault with a 1-s recovery time. The thermal inertia in the device package normally prevents the junction temperature from falling to TST within 1 s so that this 1 s fault time is not apparent to the user.

7.3.23 Fault Timer and Control

Three types of faults are recognized by the UCC29950:

  • Latching
  • Long with Auto Recovery (1 s)
  • Short with Auto Recovery (100 ms)

A latching shutdown is triggered by the following events. VCC must be cycled off and on to reset these faults:

  • VBLK < Peak of AC line. (This can happen only if there is a fault in the VBLK sensing network or an open circuit in the path between the line input and CBLK. This condition is evaluated each time the UCC29950 turns on. It is not evaluated during normal operation.)
  • At start-up the UCC29950 performs a cyclic redundancy check on its internal memory. If the device fails this check it stops immediately and will not attempt to start the power stages.

A long fault is triggered by any of the following events:

  • LLC stage Over Current Protection
  • PFC Stage Second Current Limit
  • X-Cap Discharge (This reduces average power dissipation in the high-voltage depletion mode MOSFET)
  • Over Temperature Fault (Thermal inertia increases the recovery time)

A short fault is triggered by any of the following events:

  • VCC Under Voltage
  • VAC < VAC(low_falling) (Brownout)
  • VAC > VAC(high_rising)

7.4 Device Functional Modes

7.4.1 Mode Selection

The UCC29950 may be operated in one of two modes. In Aux Bias Mode VCC is supplied from an external source. A small, separate fly-back supply is normally used for this purpose. Aux Bias Mode allows the user to turn both the LLC and PFC stages off or to run only the PFC stage or to run both PFC and LLC stages together and to run the system at no load if desired. In Self Bias Mode the VCC rail is powered from a small auxiliary winding on the LLC transformer and ON/OFF control of the PFC and LLC stages is not possible in Self Bias Mode.

7.4.2 Start-Up in Aux Bias Mode

A small external PSU is used to supply VCC in Aux Bias Mode. A 12-V 50-mA supply is normally sufficient but this does depend on system level factors such as the gate-driver circuitry used, the load presented by the switching MOSFETs and other factors.

UCC29950 aux_bias_lusc18.gifFigure 20. External Control Signal

Aux Bias Mode is selected if the MD_SEL/PS_ON pin is kept lower than VMODE(selsb) for a time greater than TMODE(sel_read) after VCC passes the VCCSTART threshold. After this time has passed, the MD_SEL/PS_ON pin may be used to turn on the PFC stage alone by setting this pin to a voltage between the VPS_ONPFC_RUN and VPS_ONLLCPFC_RUN levels. The PFC and LLC stages may both be turned on by setting the MD_SEL/PS_ON pin to a voltage greater than VPS_ONLLCPFC_RUN. Refer to the Electrical Characteristics table for the related tolerances on these thresholds.

The MD_SEL/PS_ON pin may be driven from an active source such as a comparator or digital output (with appropriate level shifting, provided by an optocoupler for example). A simple RC network may also be used if an active source is not available. Connect a capacitor from MD_SEL/PS_ON to AGND and a resistor from MD_SEL/PS_ON to VCC. The RC time constant should be chosen so that the voltage at the MD_SEL/PS_ON pin is less than VMODE_SELSB 10 ms after VCC increases past VCC(start). Normally an RC time constant of 100ms will be satisfactory. The slow rise of the MD_SEL/PS_ON signal between the VPS_ONPFC_RUN and VPS_ONLLCPFC_RUN levels increases overall start-up time by a few 100 ms.

The normal sequence in a system is that VAC is applied, MD_SEL/PS_ON is held low, VCC comes up and MD_SEL/PS_ON is then used to turn the PFC/LLC stages on as shown in Figure 21.

This sequence applies whether or not the X-Cap discharge function is being used.

Typical start-up times in Aux Bias Mode are in the range 150 ms to 250 ms after MD_SEL/PS_ON is brought high.

UCC29950 aux_bias_turnon_lusc18.gifFigure 21. Typical Aux Bias Turn-On Sequence
(both PFC and LLC stages are turned on simultaneously by pulling MD_SEL/PS_ON above VPS_ONLLCPFC_RUN )

7.4.3 Start-Up Operation in Self-Bias Mode

In Self Bias Mode, the MD_SEL/PS_ON pin should be tied to VCC as shown. The start-up FET is a normally on depletion mode device, a BSS126 for example. CVCC is charged via the start-up FET and the internal current-limiting block. Initial charging of CVCC happens automatically even though VCC is below VCCSTART. When VCC reaches VCCSTART the SUFG pin goes low, which turns the start-up FET off. If the MD_SEL/PS_ON pin is tied to VCC, the UCC29950 enters Self Bias Mode. SUFG goes high again to turn the start-up FET on again and allow CVCC to charge further. When CVCC has been charged to VCCSB(start) (typically 16.2 V) the start-up FET is turned off and providing that the current into the AC1 and AC2 pins is greater than IAC(low_rising) and that the sensed VBLK voltage is greater than peak of AC line the PFC stage is started. As noted earlier, an 18-V zener diode should be used to clamp the voltage on CVCC. The switching operation of the PFC and LLC stage is maintained as long as CVCC is above VCCSB(stop). Equation 2 allows the user to select the value of CVCC.

UCC29950 self_bias_lusc18.gifFigure 22. Self Bias Mode

The start-up time in Self Bias Mode depends strongly on the current available for charging and on the capacitance on the VCC rail and. A first pass estimate of start-up time can be made using:

Equation 2. UCC29950 qu2_lusc18.gif

For typical values, assuming CVCC is 200 µF, tSTART is therefore 1.8 s.

UCC29950 sel_bias_turnon_lusc18.gifFigure 23. Typical Self Bias Turn-On Sequence

7.4.4 Bias Rail UVLO

The UCC29950 continuously monitors the voltage at its VCC pin. It stops both the PFC and LLC stages if VCC falls below VCCAB(uvlo_stop) or VCCSB(uvlo_stop), depending on whether it is operating in Aux Bias or Self Bias Modes respectively. In Aux Bias Mode, the device simply waits for VCC to recover to a voltage greater than VCCAB(uvlo_stop). At which point it restarts. If it is operating in Self Bias Mode it sets SUFG HI to turn the start-up FET on. The current through the start-up FET then charges the capacitance on the VCC rail up to VCCSB(start) at which point the system tries to restart as described earlier.

7.4.5 LLC Stage MOSFET Drive

UCC29950 includes two high-power drivers that are capable of directly driving both MOSFETs in the half bridge LLC circuit through a suitable gate drive transformer as shown in Figure 24. Alternatively an external driver device, with its own high-side channel, can be used to interface between UCC29950 and half bridge MOSFETs as shown in Figure 25.

If a gate drive transformer is used then GD1 should be used to drive the high-side MOSFET and GD2 used to drive the low-side MOSFET. If a gate driver device is used then GD1 should be used to drive the low-side MOSFET and GD2 used to drive the high-side MOSFET. TI recommends the UCC22714 as a suitable gate driver device. The first and last LLC gate drive pulses are normally half width and appear on GD1 and GD2 respectively, see Figure 17.

UCC29950 llc_mosfet_lusc18.gifFigure 24. LLC MOSFET Gate Drive Using a Gate Drive Transformer (simplified)
UCC29950 llc_mosfet_gate_lusc18.gifFigure 25. LLC MOSFET Gate Drive Using a Driver Device (simplified)

7.4.6 Gate Drive Transformer

Gate driver transformers are robust and less susceptible to noise than gate drive devices but will also be larger than a solution using a gate driver device.

The GD1 and GD2 outputs from the UCC29950 are symmetrical, with 180˚ phase shift and a duty cycle less than 50%. If the gate drive transformer is driven as shown in Figure 24, then the waveform at its primary has no DC component. The gate-drive transformer must be able to support the maximum V sec product based on the GD1 and GD2 signal at LLC FMIN. In steady state conditions, the duty cycles of GD1 and GD2 outputs are extremely well matched, typically within 0.1% of each other. When using a gate-drive transformer, the GD1 signal should be used to driver the high-side MOSFET and the GD2 signal used to drive the low-side MOSFET, as shown in Figure 24. The initial half-width pulse on GD1 and final half-width pulse on GD2 ensures that there is no DC flux imbalance on either the gate-drive transformer or in the main transformer see Figure 17.

The gate-drive transformer used to directly drive the LLC power MOSFETs should have a low common-mode capacitance. The common-mode current that flows from the upper-gate winding, back through the UCC29950 drivers, during bridge-switching transitions must return to the power circuit via the UCC29950 GND pin. Voltage disturbance on the GND pins during LLC bridge transitions may lead to audible interaction between the PFC and LLC power stages.

Placing a screen between the controller winding and gate-drive windings is one way to reduce the common-mode capacitance of the transformer. This screen should be connected to the source of the lower half-bridge MOSFET (Q2).

The gate-drive transformer should drive both the low-side and high-side MOSFETs as shown in Figure 24. This ensures that propagation delays through the transformer are matched and the symmetry of the dead time is maintained.

7.4.7 Gate Drive Device

A gate-driver device solution is less bulky than a gate-drive transformer and may be easier to design and layout. The capacitance from output to input is very low which means that interference from common-mode currents will not normally occur. In both Aux Bias and Self Bias Modes, the HO and LO outputs must make a clean transition between their active state (where they obey the HI and LI inputs) and their UVLO state (where they are latched low). Additionally, if operating in Aux Bias Mode it is very important to make sure that the UVLO level of the gate-driver device is less than that of the UCC29950 (VCCAB_UVLO(stop)). This ensures that the GD1 and GD2 signals are always passed on to the switching MOSFETs and that the UCC29950 maintains control of the LLC power train. It also ensures, if there is a UVLO condition on the bias rail, that the UCC29950 can enter and exit the UVLO condition correctly with a proper soft start during the recovery phase. In Self Bias Mode, it is not necessary that the driver UVLO is lower than that of the UCC29950, if the MOSFET gate drives stop for any reason then the bias always collapse to the UCC29950 VCCSB_UVLO(stop) level, followed by a full restart as described in LLC Stage Soft Start.

High-side driver devices use a bootstrap capacitor, CB in Figure 25, to supply the current to charge the gate of the high side MOSFET. This capacitor must first be charged to the driver high-side UVLO voltage before any HO pulses are delivered to the high-side MOSFET gate. CB is charged during the first few LO pulses. Once the voltage across CB reaches the high side driver UVLO level there is normally a short delay, 20 µs, before HO pulses appear. The current in the circuit during the first few switching cycles, when both high-side and low-side MOSFETs are being driven, will be higher than normal. The circuit designer must ensure that the LLC power-circuit components are rated for these stresses.

7.4.8 Comparison

Users who employ a gate-drive transformer benefit from special features in UCC29950 to ensure a much smoother start-up transition of the LLC converter. This allows magnetics with a lower peak-current rating to be used safely. It is important to use a gate-drive transformer with a low common-mode capacitance.

If an external high-side driver is used then the smooth start-up feature is effectively disabled and the designer must ensure that the LLC magnetics are rated to cope with the resulting increased peak current during start-up.

Figure 26 compares the LLC resonant current waveform observed during the start-up transient. Both traces are triggered on GD1 output at the same point. The lower trace is observed when directly driving the LLC bridge MOSFETs via a gate drive transformer. The upper trace is observed when driving the LLC bridge MOSFETs via an external gate device driver. Vertical scale is 2 A/div. Horizontal scale is 10 µs/div.

UCC29950 llc_currents_lusc18.gifFigure 26. Typical LLC Transformer Primary Current During Startup