SLUSC18A September 2014 – March 2015 UCC29950
|GND||1||-||Power ground. Connect all the gate driver pulsating current returns to this pin.|
|GD2||2||O||Gate drive output for LLC stage MOSFET. The typical peak current is 1-A source, 1.6-A sink (CLOAD = 1 nF)|
|VCC||3||-||Bias supply input.|
|SUFG||4||O||Start-up MOSFET gate drive output. Leave open circuit if not used.|
|SUFS||5||I||Start-up MOSFET Source. Connect to VCC if not used.|
|AGND||6||-||Signal ground. Connect all device control signal returns to this ground.|
|MD_SEL/PS_ON||7||I||Dual function pin:
|VBULK||8||I||Voltage sense input for PFC stage output.|
|AC2||9||I||AC line voltage detection. Connect 9.3 MΩ between AC line and this pin.|
|AC1||10||I||AC line voltage detection. Connect 9.3 MΩ between AC line and this pin.|
|LLC_CS||11||I||Current sense input for the LLC stage.|
|FB||12||I||Feedback signal input for LLC stage.|
|PFC_CS||13||I||Current sense input for the PFC stage.|
|GD1||14||O||Gate drive output for LLC stage MOSFET. The typical peak current is 1-A source, 1.6-A sink (CLOAD = 1 nF).|
|AC_DET||15||O||AC line voltage fail signal output, for system use.|
|PFC_GD||16||O||The typical peak current is 0.6-A source, 1.3-A sink (CLOAD = 1 nF).|
The VCC pin is the power supply input terminal to the device. This pin should be decoupled with a 10-μF ceramic bypass capacitor in both Aux Bias and Self Bias Modes. An additional hold-up capacitor is needed at this pin if operating in Self Bias Mode.
MD_SEL/PS_ON pin. This pin can be used to make the UCC29950 operate in Self Bias or Auxiliary Bias Mode. If MD_SEL/PS_ON pin is high during start up the controller enters Self Bias Mode. In this mode, the capacitor on the device’s VCC rail is charged by an external depletion mode MOSFET connected at the SUFS and SUFG pins. Once the VCC rail reaches an appropriate operating voltage, the FET is turned off and the VCC rail is then supplied from an auxiliary winding on the LLC transformer. This avoids the standing or static losses incurred if a drop resistor from rectified AC line were used to charge the VCC rail during startup.
If the MD_SEL/PS_ON pin is held low for at least 10 ms during start up the UCC29950 enters Aux Bias Mode. Once this time has passed this pin may be used to turn on the PFC stage on its own or both the PFC and LLC stages according to the values given in the MD_SEL/PS_ON part of the Electrical Characteristics.
The SUFG and SUFS are the control pins for an external start-up depletion mode FET. The use of a switched device here eliminates the static power dissipation in a conventional resistive start-up approach where a drop resistor from the rectified AC line to VCC is typically used. As a result standby power consumption is reduced.
Connect the FET gate to SUFG and its source to SUFS. The drain of the FET is connected to the rectified AC voltage. SUFG and SUFS control the initial charging of the capacitor on the VCC rail during start-up in the Self-Bias mode of operation. In this mode SUFG tracks SUFS as CVCC is charged and VCC rises. When VCC reaches VCCSB(start) (typically 16.2 V) SUFG goes low. This turns the start-up FET off and the PFC and LLC gate outputs start running. SUFG remains low unless VCC falls below VCCSB_UVLO(stop) (typically 7.9 V) or an X-Cap discharge is required. If VCC falls below VCCSB_UVLO(stop) then SUFG goes high to turn the start-up FET on and recharge CVCC back up to VCCSB_START.
SUFG and SUFS also provide an X-Cap discharge function in both Aux Bias and Self Bias Modes. This function is described fully in Active X-Cap Discharge.
If the UCC29950 is used in Aux Bias Mode then VCC is supplied by an external source and the external depletion mode FET is used only to provide the X-Cap discharge function. SUFG is at 0 V after a time TMODE_SEL_READ has elapsed during power up after CVCC exceeds VCCSTART. SUFG goes high whenever an X-Cap discharge is required. If the start up FET is not used and X-Cap discharge is not desired then SUFS should be connected to VCC and SUFG should be left open circuit.
GD1 and GD2 are the LLC gate drive outputs for the LLC half-bridge power MOSFETs. A gate drive transformer or other suitable device is required to generate a floating drive for the high-side MOSFET. The first and last LLC gate drive pulses are normally half width and appear on GD1 and GD2 respectively. If the LLC_OCP3 level is exceeded then the final pulse is of normal width. The typical peak current is 1-A source, 1.6-A sink (1-nF load).
GND is the power ground for the device. Connect all the gate-driver pulsating current returns to this pin.
AGND is the signal ground for device control signals. Connect all control signal returns to this pin.
LLC_CS is the LLC stage current sense input. LLC_CS is used for LLC stage over-load protection. The load current is reflected to the primary side of the transformer where it is sensed using a resistor. The UCC29950 senses the LLC stage input current level and enters the over-current protection Shut-Down Mode when the current-sense signal exceeds the current and time thresholds described in LLC Three Level Over-Current Protection. The controller tries to resume operation at 1-s intervals.
FB is the LLC stage control-loop feedback input. Connect the opto-coupler emitter to this pin. The FB pin is the input to the internal VCO. The VCO generates the switching frequency of the LLC converter. GD1 and GD2 stop switching if this pin is driven above VFB_LLC(off) (typically 3.75 V) and resume operation when it falls below VFB(max) (typically 3.0 V). If this pin is held below VFB(min) (typically 200 mV) the GD1 and GD2 outputs runs at their minimum frequency.
PFC_GD is the gate-driver output for a PFC MOSFET. Connect the PFC MOSFET gate through a resistor to control its switching speed. Because of the limited driving capability an external gate driver might be needed to support certain power MOSFET input capacitance conditions. The typical peak current is 0.6-A source, 1.3-A sink (CLOAD = 1 nF).
PFC_CS is the current sense input for the PFC stage. It is recommended to add a current-limiting resistor between the current-sense resistor and current-sense pin, to prevent damage during inrush conditions. A 1-kΩ resistor normally suffices. The UCC29950 implements a new hybrid average current-control method which controls the average current but uses the peak PFC_CS signal to terminate each switching cycle (see Hybrid PFC Control Loop). Correct PCB layout is important to ensure that the signal at this pin is an accurate representation of the current being controlled.
The VBULK pin is used for PFC output-voltage sensing. Connect the sensing resistors to this pin. The upper resistor in the potential divider must be 30 MΩ and the lower resistor must be 73.3 kΩ. The high impedance reduces the static power dissipation.
AC1 and AC2 are the AC line voltage sensing inputs. The UCC29950 uses differential sensing for more accurate measurement of line voltage. These pins must be connected to the two line inputs via 9.3-MΩ resistors.
The AC_DET is a system-level signal which may be used for indication and system control. AC_DET goes high if the instantaneous AC voltage remains below the brownout level for longer than 32 ms. An opto-coupler can be used to send a signal to a system supervisor device so that appropriate action can be taken. In order to provide hold-up time to the system, the power stages continue to operate for 100 ms after AC_DET goes high. This behavior is shown in Figure 10, Figure 11 and Figure 12.