SLUSC18A September   2014  – March 2015 UCC29950


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1. 5.1 Detailed Pin Descriptions
      1. 5.1.1  VCC
      2. 5.1.2  MD_SEL/PS_ON
      3. 5.1.3  SUFG, SUFS
      4. 5.1.4  GD1, GD2
      5. 5.1.5  GND
      6. 5.1.6  AGND
      7. 5.1.7  LLC_CS
      8. 5.1.8  FB
      9. 5.1.9  PFC_GD
      10. 5.1.10 PFC_CS
      11. 5.1.11 VBULK
      12. 5.1.12 AC1, AC2
      13. 5.1.13 AC_DET
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Storage Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Sense Networks
      2. 7.3.2  Sense Network Fault Detection
      3. 7.3.3  PFC Stage Soft-Start
      4. 7.3.4  AC Line Voltage Sensing
      5. 7.3.5  VBLK Sensing
      6. 7.3.6  AC Input UVLO and Brownout Protection
      7. 7.3.7  Dither
      8. 7.3.8  Active X-Cap Discharge
      9. 7.3.9  LLC Stage Soft Start
      10. 7.3.10 PFC Stage Current Sensing
      11. 7.3.11 Input Power Limit
      12. 7.3.12 PFC Stage Soft Start
      13. 7.3.13 Hybrid PFC Control Loop
      14. 7.3.14 PFC Stage Second Current Limit
      15. 7.3.15 PFC Inductor and Bulk Capacitor Recommendations
      16. 7.3.16 PFC Stage Over Voltage Protection
      17. 7.3.17 LLC Stage Control
      18. 7.3.18 Driver Output Stages and Characteristic
      19. 7.3.19 LLC Stage Dead Time Profile
      20. 7.3.20 LLC Stage Current Sensing
      21. 7.3.21 LLC Three Level Over-Current Protection
      22. 7.3.22 Over-Temperature Protection
      23. 7.3.23 Fault Timer and Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Selection
      2. 7.4.2 Start-Up in Aux Bias Mode
      3. 7.4.3 Start-Up Operation in Self-Bias Mode
      4. 7.4.4 Bias Rail UVLO
      5. 7.4.5 LLC Stage MOSFET Drive
      6. 7.4.6 Gate Drive Transformer
      7. 7.4.7 Gate Drive Device
      8. 7.4.8 Comparison
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  LLC Stage
        2.  LLC Switching Frequency
        3.  LLC Transformer Turns Ratio
        4.  LLC Stage Equivalent Load Resistance
        5.  LLC Gain Range
        6.  Select LN and QE
        7.  LLC No-Load Gain
        8.  Parameters of the LLC Resonant Circuit
        9.  Verify the LLC Resonant Circuit Design
        10. LLC Primary-Side Currents
        11. LLC Secondary-Side Currents
        12. LLC Transformer
        13. LLC Resonant Inductor
        14. Combining the LLC Resonant Inductor and Transformer
        15. LLC Resonant Capacitor
        16. LLC Stage with Split Resonant Capacitor
        17. LLC Primary-Side MOSFETs
        18. LLC Output Rectifier Diodes
        19. LLC Stage Output Capacitors
        20. LLC Stage Over-Current Protection, Current Sense Resistor
        21. Detailed Design Procedure for the PFC stage
        22. PFC Stage Output Current Calculation
        23. Line Current Calculation
        24. Bridge Rectifier
        25. PFC Boost Inductor
        26. PFC Input Capacitor
        27. PFC Stage MOSFET
        28. PFC Boost Diode
        29. Bulk Capacitor
        30. PFC Stage Current Sense Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  GND Pin
      2. 10.1.2  GD1, GD2 Pins
      3. 10.1.3  VCC Pin
      4. 10.1.4  SUFG Pin
      5. 10.1.5  SUFS Pin
      6. 10.1.6  AGND Pin
      7. 10.1.7  MD_SEL/PS_ON Pin
      8. 10.1.8  VBULK Pin
      9. 10.1.9  AC1, AC2 Pins
      10. 10.1.10 LLC_CS
      11. 10.1.11 FB
      12. 10.1.12 PFC_CS
      13. 10.1.13 AC_DET
      14. 10.1.14 PFC_GD
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

16 Pins
Top View
UCC29950 pin_lusc18.gif

Pin Functions

GND 1 - Power ground. Connect all the gate driver pulsating current returns to this pin.
GD2 2 O Gate drive output for LLC stage MOSFET. The typical peak current is 1-A source, 1.6-A sink (CLOAD = 1 nF)
VCC 3 - Bias supply input.
SUFG 4 O Start-up MOSFET gate drive output. Leave open circuit if not used.
SUFS 5 I Start-up MOSFET Source. Connect to VCC if not used.
AGND 6 - Signal ground. Connect all device control signal returns to this ground.
MD_SEL/PS_ON 7 I Dual function pin:
  1. Mode Select Function (MD_SEL): Select self bias or Aux bias mode of operation.
  2. Power Supply On Function (PS_ON): Stop/start control of PFC and LLC stages, Aux Bias mode only.
VBULK 8 I Voltage sense input for PFC stage output.
AC2 9 I AC line voltage detection. Connect 9.3 MΩ between AC line and this pin.
AC1 10 I AC line voltage detection. Connect 9.3 MΩ between AC line and this pin.
LLC_CS 11 I Current sense input for the LLC stage.
FB 12 I Feedback signal input for LLC stage.
PFC_CS 13 I Current sense input for the PFC stage.
GD1 14 O Gate drive output for LLC stage MOSFET. The typical peak current is 1-A source, 1.6-A sink (CLOAD = 1 nF).
AC_DET 15 O AC line voltage fail signal output, for system use.
PFC_GD 16 O The typical peak current is 0.6-A source, 1.3-A sink (CLOAD = 1 nF).

5.1 Detailed Pin Descriptions

5.1.1 VCC

The VCC pin is the power supply input terminal to the device. This pin should be decoupled with a 10-μF ceramic bypass capacitor in both Aux Bias and Self Bias Modes. An additional hold-up capacitor is needed at this pin if operating in Self Bias Mode.

5.1.2 MD_SEL/PS_ON

MD_SEL/PS_ON pin. This pin can be used to make the UCC29950 operate in Self Bias or Auxiliary Bias Mode. If MD_SEL/PS_ON pin is high during start up the controller enters Self Bias Mode. In this mode, the capacitor on the device’s VCC rail is charged by an external depletion mode MOSFET connected at the SUFS and SUFG pins. Once the VCC rail reaches an appropriate operating voltage, the FET is turned off and the VCC rail is then supplied from an auxiliary winding on the LLC transformer. This avoids the standing or static losses incurred if a drop resistor from rectified AC line were used to charge the VCC rail during startup.

If the MD_SEL/PS_ON pin is held low for at least 10 ms during start up the UCC29950 enters Aux Bias Mode. Once this time has passed this pin may be used to turn on the PFC stage on its own or both the PFC and LLC stages according to the values given in the MD_SEL/PS_ON part of the Electrical Characteristics.

5.1.3 SUFG, SUFS

The SUFG and SUFS are the control pins for an external start-up depletion mode FET. The use of a switched device here eliminates the static power dissipation in a conventional resistive start-up approach where a drop resistor from the rectified AC line to VCC is typically used. As a result standby power consumption is reduced.

Connect the FET gate to SUFG and its source to SUFS. The drain of the FET is connected to the rectified AC voltage. SUFG and SUFS control the initial charging of the capacitor on the VCC rail during start-up in the Self-Bias mode of operation. In this mode SUFG tracks SUFS as CVCC is charged and VCC rises. When VCC reaches VCCSB(start) (typically 16.2 V) SUFG goes low. This turns the start-up FET off and the PFC and LLC gate outputs start running. SUFG remains low unless VCC falls below VCCSB_UVLO(stop) (typically 7.9 V) or an X-Cap discharge is required. If VCC falls below VCCSB_UVLO(stop) then SUFG goes high to turn the start-up FET on and recharge CVCC back up to VCCSB_START.

SUFG and SUFS also provide an X-Cap discharge function in both Aux Bias and Self Bias Modes. This function is described fully in Active X-Cap Discharge.

If the UCC29950 is used in Aux Bias Mode then VCC is supplied by an external source and the external depletion mode FET is used only to provide the X-Cap discharge function. SUFG is at 0 V after a time TMODE_SEL_READ has elapsed during power up after CVCC exceeds VCCSTART. SUFG goes high whenever an X-Cap discharge is required. If the start up FET is not used and X-Cap discharge is not desired then SUFS should be connected to VCC and SUFG should be left open circuit.

5.1.4 GD1, GD2

GD1 and GD2 are the LLC gate drive outputs for the LLC half-bridge power MOSFETs. A gate drive transformer or other suitable device is required to generate a floating drive for the high-side MOSFET. The first and last LLC gate drive pulses are normally half width and appear on GD1 and GD2 respectively. If the LLC_OCP3 level is exceeded then the final pulse is of normal width. The typical peak current is 1-A source, 1.6-A sink (1-nF load).

5.1.5 GND

GND is the power ground for the device. Connect all the gate-driver pulsating current returns to this pin.

5.1.6 AGND

AGND is the signal ground for device control signals. Connect all control signal returns to this pin.

5.1.7 LLC_CS

LLC_CS is the LLC stage current sense input. LLC_CS is used for LLC stage over-load protection. The load current is reflected to the primary side of the transformer where it is sensed using a resistor. The UCC29950 senses the LLC stage input current level and enters the over-current protection Shut-Down Mode when the current-sense signal exceeds the current and time thresholds described in LLC Three Level Over-Current Protection. The controller tries to resume operation at 1-s intervals.

5.1.8 FB

FB is the LLC stage control-loop feedback input. Connect the opto-coupler emitter to this pin. The FB pin is the input to the internal VCO. The VCO generates the switching frequency of the LLC converter. GD1 and GD2 stop switching if this pin is driven above VFB_LLC(off) (typically 3.75 V) and resume operation when it falls below VFB(max) (typically 3.0 V). If this pin is held below VFB(min) (typically 200 mV) the GD1 and GD2 outputs runs at their minimum frequency.

5.1.9 PFC_GD

PFC_GD is the gate-driver output for a PFC MOSFET. Connect the PFC MOSFET gate through a resistor to control its switching speed. Because of the limited driving capability an external gate driver might be needed to support certain power MOSFET input capacitance conditions. The typical peak current is 0.6-A source, 1.3-A sink (CLOAD = 1 nF).

5.1.10 PFC_CS

PFC_CS is the current sense input for the PFC stage. It is recommended to add a current-limiting resistor between the current-sense resistor and current-sense pin, to prevent damage during inrush conditions. A 1-kΩ resistor normally suffices. The UCC29950 implements a new hybrid average current-control method which controls the average current but uses the peak PFC_CS signal to terminate each switching cycle (see Hybrid PFC Control Loop). Correct PCB layout is important to ensure that the signal at this pin is an accurate representation of the current being controlled.

5.1.11 VBULK

The VBULK pin is used for PFC output-voltage sensing. Connect the sensing resistors to this pin. The upper resistor in the potential divider must be 30 MΩ and the lower resistor must be 73.3 kΩ. The high impedance reduces the static power dissipation.

5.1.12 AC1, AC2

AC1 and AC2 are the AC line voltage sensing inputs. The UCC29950 uses differential sensing for more accurate measurement of line voltage. These pins must be connected to the two line inputs via 9.3-MΩ resistors.

5.1.13 AC_DET

The AC_DET is a system-level signal which may be used for indication and system control. AC_DET goes high if the instantaneous AC voltage remains below the brownout level for longer than 32 ms. An opto-coupler can be used to send a signal to a system supervisor device so that appropriate action can be taken. In order to provide hold-up time to the system, the power stages continue to operate for 100 ms after AC_DET goes high. This behavior is shown in Figure 10, Figure 11 and Figure 12.