SLUSC18A September   2014  – March 2015 UCC29950


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1. 5.1 Detailed Pin Descriptions
      1. 5.1.1  VCC
      2. 5.1.2  MD_SEL/PS_ON
      3. 5.1.3  SUFG, SUFS
      4. 5.1.4  GD1, GD2
      5. 5.1.5  GND
      6. 5.1.6  AGND
      7. 5.1.7  LLC_CS
      8. 5.1.8  FB
      9. 5.1.9  PFC_GD
      10. 5.1.10 PFC_CS
      11. 5.1.11 VBULK
      12. 5.1.12 AC1, AC2
      13. 5.1.13 AC_DET
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Storage Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Sense Networks
      2. 7.3.2  Sense Network Fault Detection
      3. 7.3.3  PFC Stage Soft-Start
      4. 7.3.4  AC Line Voltage Sensing
      5. 7.3.5  VBLK Sensing
      6. 7.3.6  AC Input UVLO and Brownout Protection
      7. 7.3.7  Dither
      8. 7.3.8  Active X-Cap Discharge
      9. 7.3.9  LLC Stage Soft Start
      10. 7.3.10 PFC Stage Current Sensing
      11. 7.3.11 Input Power Limit
      12. 7.3.12 PFC Stage Soft Start
      13. 7.3.13 Hybrid PFC Control Loop
      14. 7.3.14 PFC Stage Second Current Limit
      15. 7.3.15 PFC Inductor and Bulk Capacitor Recommendations
      16. 7.3.16 PFC Stage Over Voltage Protection
      17. 7.3.17 LLC Stage Control
      18. 7.3.18 Driver Output Stages and Characteristic
      19. 7.3.19 LLC Stage Dead Time Profile
      20. 7.3.20 LLC Stage Current Sensing
      21. 7.3.21 LLC Three Level Over-Current Protection
      22. 7.3.22 Over-Temperature Protection
      23. 7.3.23 Fault Timer and Control
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mode Selection
      2. 7.4.2 Start-Up in Aux Bias Mode
      3. 7.4.3 Start-Up Operation in Self-Bias Mode
      4. 7.4.4 Bias Rail UVLO
      5. 7.4.5 LLC Stage MOSFET Drive
      6. 7.4.6 Gate Drive Transformer
      7. 7.4.7 Gate Drive Device
      8. 7.4.8 Comparison
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  LLC Stage
        2.  LLC Switching Frequency
        3.  LLC Transformer Turns Ratio
        4.  LLC Stage Equivalent Load Resistance
        5.  LLC Gain Range
        6.  Select LN and QE
        7.  LLC No-Load Gain
        8.  Parameters of the LLC Resonant Circuit
        9.  Verify the LLC Resonant Circuit Design
        10. LLC Primary-Side Currents
        11. LLC Secondary-Side Currents
        12. LLC Transformer
        13. LLC Resonant Inductor
        14. Combining the LLC Resonant Inductor and Transformer
        15. LLC Resonant Capacitor
        16. LLC Stage with Split Resonant Capacitor
        17. LLC Primary-Side MOSFETs
        18. LLC Output Rectifier Diodes
        19. LLC Stage Output Capacitors
        20. LLC Stage Over-Current Protection, Current Sense Resistor
        21. Detailed Design Procedure for the PFC stage
        22. PFC Stage Output Current Calculation
        23. Line Current Calculation
        24. Bridge Rectifier
        25. PFC Boost Inductor
        26. PFC Input Capacitor
        27. PFC Stage MOSFET
        28. PFC Boost Diode
        29. Bulk Capacitor
        30. PFC Stage Current Sense Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  GND Pin
      2. 10.1.2  GD1, GD2 Pins
      3. 10.1.3  VCC Pin
      4. 10.1.4  SUFG Pin
      5. 10.1.5  SUFS Pin
      6. 10.1.6  AGND Pin
      7. 10.1.7  MD_SEL/PS_ON Pin
      8. 10.1.8  VBULK Pin
      9. 10.1.9  AC1, AC2 Pins
      10. 10.1.10 LLC_CS
      11. 10.1.11 FB
      12. 10.1.12 PFC_CS
      13. 10.1.13 AC_DET
      14. 10.1.14 PFC_GD
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

In order to increase the reliability and robustness of the design, it is recommended that the following layout guidelines be met.

10.1.1 GND Pin

  • This pin is the power ground connection and should be used as the return connection for the driver pins PFC_GD, GD1 and GD2.
  • GND and AGND must be connected at a star point close to the pins on the controller
  • If possible use a ground plane to minimize noise pickup.

10.1.2 GD1, GD2 Pins

  • The GD1 and GD2 gate drive pins can be used to directly drive the primary winding of a gate-drive transformer or a high voltage gate driver device. The tracks connected to these pins carry high dv/dt signals. Minimize noise pickup by routing them as far away as possible from tracks connected to the device inputs, AC1, AC2, VBULK, FB, PFC_CS and LLC_CS.

10.1.3 VCC Pin

  • The VCC pin must be decoupled to GND and AGND by two 10-µF 1206 ceramic capacitors placed close to the pins. In addition it is recommended that an additional 0.1-µF ceramic capacitor 0603 be placed in parallel between the VCC and AGND pin.

10.1.4 SUFG Pin

  • The SUFG is a high-impedance pin and can only be connected to the gate of the external depletion mode MOSFET when the external high-voltage start-up feature is required. If the application does not require the external high-voltage start-up circuit then the SUFG pin should be left open circuit.

10.1.5 SUFS Pin

  • The SUFS connects to the source of an external depletion mode MOSFET, if this feature in not required, SUFS should be connected to the VCC rail.

10.1.6 AGND Pin

  • As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the integrity of the ground return. Place all decoupling and filter capacitors as close as possible to the device pins with short traces. The AGND pin is used as the return connection for the low-power signaling and sensitive signal traces, AC1, AC2, VBULK, FB, MD_SEL/PS_ON and AC DET. It is also used as local decoupling return for PFC_CS and LLC_CS. It is connected to the GND pin at a star point close to the device.

10.1.7 MD_SEL/PS_ON Pin

  • This pin is not especially sensitive but minimize coupling to tracks carrying high dv/dt signals.

10.1.8 VBULK Pin

  • The VBULK sense chain is connected to the high-voltage rail on the PFC stage. Typically the top resistive element of the sense chain is split into two or three separate resistors to reduce the voltage stress on each device and permit the use of standard low-cost resistors, such as 1206 sized SMT devices, in the sense chain. Sufficient PCB spacing must be given between the high-voltage connections to the low voltage and GND nets. The VBULK is a high-impedance connection and should be shielded by a ground plane from any high-voltage switching nets. The copper area connecting the VBULK pin to the lower resistor/filter capacitor and the last resistor in the high-side divider chain should be kept to a minimum to reduce parasitic capacitance to any nearby switching nets. The bottom resistor in the divider network and filter capacitor must be placed close to the VBULK pin.

10.1.9 AC1, AC2 Pins

  • The AC1 and AC2 are connected to the AC input lines by resistive divider chains. These divider chains are normally formed using several discrete resistors in series. The AC1 and AC2 are high-impedance pins and care must be taken to route the resistor divider components away from high voltage switching nets. Ideally the connections should be shielded by ground planes. Sufficient PCB spacing must be given between the high-voltage connections and any low-voltage nets. A filter capacitor, 470 pF, must be placed in close proximity to the pins on the controller to decouple any high-frequency noise picked up on the AC1 and AC2 sense-chain connections.

10.1.10 LLC_CS

  • The LLC_CS pin should be decoupled by an external RC filter placed close to the pin. Suitable values are a 2.2-kΩ resistor and 0.1-µF ceramic capacitor.

10.1.11 FB

  • The FB signal is a low-power, high-impedance signal from the LLC regulation circuit. The PCB tracks from the opto-coupler should be tracked to minimize the loop area by running the VÌ feed track and FB signal from the opto-coupler in parallel. It is also recommended to provide screening for these traces with ground plane(s).

10.1.12 PFC_CS

  • The PFC_CS requires an external resistor, recommended value of 1 kΩ, between the current sensing resistor and the PFC_CS pin to avoid overstressing the device during inrush. A small filter capacitor (1 nF) may be useful to further reduce the noise level at this pin. These components should be placed close to PFC_CS pin.
  • The PFC_CS resistor is a low resistance part. Be careful that the connections to this resistor connect directly to the part terminals to avoid adding extra parasitic resistance. Be especially careful of the connection to the ground side of this resistor.

10.1.13 AC_DET

  • The AC_DET is a signal output. This is a low-voltage signal trace and must be kept clear of any high-voltage switching nodes.

10.1.14 PFC_GD

  • The track connected to the PFC_GD pin carries high dv/dt signal. Minimize noise pickup by routing the trace to this pin as far away as possible from tracks connected to the device inputs – AC1, AC2, VBULK, FB, PFC_CS and LLC_CS

10.2 Layout Example

UCC29950 layout_lusc18.gifFigure 43.