SLUSDR3B June   2019  – February 2024 UCC5390-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications for DWV Package
    7. 5.7  Safety-Related Certifications For DWV Package
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 6.1.1 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
    4. 7.4 Device Functional Modes
      1. 7.4.1 ESD Structure
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Designing IN+ and IN– Input Filter
        2. 8.2.2.2 Gate-Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
        4. 8.2.2.4 Estimating Junction Temperature
      3. 8.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 8.2.3.1 Selecting a VCC1 Capacitor
        2. 8.2.3.2 Selecting a VCC2 Capacitor
        3. 8.2.3.3 Application Circuits With Output Stage Negative Bias
      4. 8.2.4 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PCB Material
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Certifications
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Electrical Characteristics

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL = 100-pF, TJ = –40°C to +125°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCC1 Input supply quiescent current 1.67 2.4 mA
IVCC2 Output supply quiescent current 1.1 1.8 mA
SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VIT+(UVLO1) VCC1 Positive-going UVLO threshold voltage 2.6 2.8 V
VIT– (UVLO1) VCC1 Negative-going UVLO threshold voltage 2.4 2.5 V
Vhys(UVLO1) VCC1 UVLO threshold hysteresis 0.1 V
OUTPUT SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VIT+(UVLO2) VCC2 Positive-going UVLO threshold voltage 12 13 V
VIT–(UVLO2) VCC2 Negative-going UVLO threshold voltage 10.3 11.0 V
Vhys(UVLO2) VCC2 UVLO threshold voltage hysteresis 1 V
LOGIC I/O
VIT+(IN) Positive-going input threshold voltage (IN+, IN–) 0.55 × VCC1 0.7 × VCC1 V
VIT–(IN) Negative-going input threshold voltage (IN+, IN–) 0.3 × VCC1 0.45 × VCC1 V
Vhys(IN) Input hysteresis voltage (IN+, IN–) 0.1 × VCC1 V
IIH High-level input leakage at IN+ IN+ = VCC1 40 240 µA
IIL Low-level input leakage at IN– IN– = GND1 –240 –40 µA
IN– = GND1 – 5 V –310 –80
GATE DRIVER STAGE
VOH High-level output voltage (OUT) IOUT = –20 mA VCC2 – 0.1 VCC2 – 0.24 V
VOL Low level output voltage (OUT) IN+ = low, IN– = high; IO = 20 mA 2 3 mV
IOH Peak source current IN+ = high, IN– = low 10 17 A
IOL Peak sink current IN+ = low, IN– = high 10 17 A
SHORT CIRCUIT CLAMPING
VCLP-OUT Clamping voltage
(VOUT –VCC2)		 IN+ = high, IN– = low, tCLAMP = 10 µs,
IOUT= 500 mA		 1 1.3 V
VCLP-OUT Clamping voltage
( VEE2 – VOUT)		 IN+ = low, IN– = high, tCLAMP = 10 µs,
IOUT = –500 mA		 1.5 V
IN+ = low, IN– = high,
IOUT = –20 mA		 0.9 1
ACTIVE PULLDOWN
VOUTSD Active pulldown voltage on OUT IOUT = 0.1 × IOUT(typ), VCC2 = open 1.8 2.5 V