Product details


Number of channels (#) 1 Isolation rating (Vrms) 5000 Power switch IGBT, SiCFET Peak output current (A) 17 DIN V VDE V 0884-10 transient overvoltage rating (Vpk) 7000 DIN V VDE V 0884-10 working voltage (Vpk) 2121 Output VCC/VDD (Max) (V) 33 Output VCC/VDD (Min) (V) 13.2 Input VCC (Min) (V) 3 Input VCC (Max) (V) 15 Prop delay (ns) 65 Operating temperature range (C) -40 to 125 open-in-new Find other Isolated gate drivers

Package | Pins | Size

SOIC (DWV) 8 67 mm² 5.85 x 11.5 open-in-new Find other Isolated gate drivers


  • 5-kVRMS single channel isolated gate driver
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1
    • HBM ESD classification level H2
    • CDM ESD classification level C6
  • 12-V UVLO referenced to GND2
  • 8-pin DWV (8.5mm creepage) package
  • 60-ns (typical) propagation delay
  • Small part-to-part skew in propagation delay
  • 100-V/ns minimum CMTI
  • 10-A minimum peak current
  • 3-V to 15-V input supply voltage
  • Up to 33-V driver supply voltage
  • Negative 5-V handling capability on input pins
  • Safety-related certifications:
    • 7000-VPK isolation (DWV) per DIN V VDE V 0884-11:2017-01 (planned)
    • 5000-VRMS (DWV) isolation rating for 1 minute per UL 1577
    • CQC Certification per GB4943.1-2011
  • CMOS inputs
  • Operating junction temperature: –40°C to +150°C

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The UCC5390-Q1 is a single-channel, isolated gate driver with 10-A source and 10-A sink peak current designed to drive MOSFETs, IGBTs, and SiC MOSFETs. The UCC5390-Q1 has its UVLO2 referenced to GND2, which facilitates bipolar supplies and optimizes SiC and IGBT switching behavior and robustness.

The UCC5390-Q1 is available in 8.5 mm SOIC-8 (DWV) package and can support isolation voltage up to 5-kVRMS. The input side is isolated from the output side with SiO2 capacitive isolation technology with longer than 40 years isolation barrier lifetime. With its high drive strength and true UVLO detection, this device is a good fit for driving IGBTs and SiC MOSFETs in applications such as on-board chargers and traction inverters.

Compared to an optocoupler, the UCC5390-Q1 has lower part-to-part skew, lower propagation delay, higher operating temperature, and higher CMTI.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 6
Type Title Date
* Datasheet UCC5390-Q1 Single-Channel Isolated Gate Driver for SiC/IGBT and Automotive Applications datasheet (Rev. A) Sep. 19, 2019
More literature UL Certification E181974 Vol 4. Sec 7 (Rev. B) Jul. 22, 2019
Technical articles How to achieve higher system robustness in DC drives, part 3: minimum input pulse Sep. 19, 2018
Technical articles How to achieve higher system robustness in DC drives, part 2: interlock and deadtime May 30, 2018
Technical articles Boosting efficiency for your solar inverter designs May 24, 2018
Technical articles How to achieve higher system robustness in DC drives, part 1: negative voltage Apr. 17, 2018

Design & development

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Hardware development

document-generic User guide
UCC5390ECDWVEVM is designed for evaluating the UCC53xxDWV family, which is a 5.0-kVRMS Isolated Single-Channel Gate Driver with 10-A source and 10-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component (...)
  • High performance driver with input and output interface
  • Ability to test most data sheet parameters
  • Ability to compare performance of various drivers with compatible pinout

Design tools & simulation

SLLM366.ZIP (53 KB) - PSpice Model
SLLM369.ZIP (3 KB) - PSpice Model
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
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