SLUSC66E March   2015  – February 2017 UCD3138A


  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Device Comparison
    1. 2.1 Product Selection Matrix
  3. Pin Configuration and Functions
    1. 3.1 UCD3138A RGC Package
    2. 3.2 UCD3138A RMH Package
    3. 3.3 UCD3138A RJA Package
  4. Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 PMBus/SMBus/I2C Timing
    7. 4.7 Peripherals
      1. 4.7.1 Digital Power Peripherals (DPPs)
        1. Front End
        2. DPWM Module
        3. DPWM Events
        4. High Resolution DPWM
        5. Oversampling
        6. DPWM Interrupt Generation
        7. DPWM Interrupt Scaling/Range
        8. DPWM Synchronization
        9. Synchronous Rectifier Dead-Time Optimization Peripheral
    8. 4.8 Typical Temperature Characteristics
  5. Parametric Measurements Information
    1. 5.1 Power-On Reset (POR) and Brown-Out Reset (BOR)
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
      1. 6.3.1 CPU Memory Map and interruptions
      2. 6.3.2 Boot ROM
      3. 6.3.3 Customer Boot Program
      4. 6.3.4 Flash Management
    4. 6.4 System Module
      1. 6.4.1 Address Decoder (DEC)
      2. 6.4.2 Memory Management Controller (MMC)
      3. 6.4.3 System Management (SYS)
      4. 6.4.4 Central Interrupt Module (CIM)
    5. 6.5 Feature Description
      1. 6.5.1  Sync FET Ramp and IDE Calculation
      2. 6.5.2  Automatic Mode Switching
        1. Phase Shifted Full Bridge Example
        2. LLC Example
        3. Mechanism for Automatic Mode Switching
      3. 6.5.3  DPWMC, Edge Generation, IntraMux
      4. 6.5.4  Filter
        1. Loop Multiplexer
        2. Fault Multiplexer
      5. 6.5.5  Communication Ports
        1. SCI (UART) Serial Communication Interface
        2. PMBus Interfacte
        3. General Purpose ADC12
        4. Timers
          1. 24-bit PWM Timer
          2. 16-Bit PWM Timers
          3. Watchdog Timer
      6. 6.5.6  Miscellaneous Analog
      7. 6.5.7  Package ID Information
      8. 6.5.8  Brownout
      9. 6.5.9  Global I/O
      10. 6.5.10 Temperature Sensor Control
      11. 6.5.11 I/O Mux Control
      12. 6.5.12 Current Sharing Control
      13. 6.5.13 Temperature Reference
  7. Device Functional Modes
    1. 7.1 Normal Mode
    2. 7.2 DPWM Multiple Output Mode
    3. 7.3 DPWM Resonant Mode
    4. 7.4 Triangular Mode
    5. 7.5 Leading Edge Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. PCMC (Peak Current Mode Control) PSFB (Phase-Shifted Full Bridge) Hardware Configuration Overview
        2. DPWM Initialization for PSFB
      3. 8.2.3 Fixed Signals to Bridge
      4. 8.2.4 Dynamic Signals to Bridge
      5. 8.2.5 System Initialization for PCM
        1. Use of Front Ends and Filters in PSFB
        2. Peak Current Detection
        3. Peak Current Mode (PCM)
      6. 8.2.6 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Decoupling and Bulk Capacitors
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. Tools and Documentation
    2. 11.2 Documentation Support
      1. 11.2.1 References
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical Packaging and Orderable Information
    1. 12.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
Input voltage V33D to DGND –0.3 3.8 V
V33DIO to DGND –0.3 3.8 V
V33A to AGND –0.3 3.8 V
BP18 to DGND –0.3 2.5 V
Ground difference, |DGND – AGND| 0.3 V
Applied to all pins, excluding AGND (2) –0.3 3.8 V
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Referenced to DGND

ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
VV33D Digital power 3 3.3 3.6 V
VV33DIO Digital I/O power 3 3.3 3.6 V
VV33A Analog power 3 3.3 3.6 V
VBP18 1.8-V digital power 1.6 1.8 2 V
TJ Junction temperature –40 125 °C

Thermal Information

64 PIN 40 PIN 40 PIN
RθJA Junction-to-ambient thermal resistance 25.1 31.0 30.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.5 16.5 13.5 °C/W
RθJB Junction-to-board thermal resistance 4.6 6.3 4.9 °C/W
ψJT Junction-to-top characterization parameter 0.2 0.2 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.6 6.3 4.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 1.1 0.7 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report,

Electrical Characteristics

3 V ≤ VV33A = VV33D = VV33DIO ≤ to 3.6 V, 1 μF of capacitance from BP18 to DGND, –40°C ≤ TJ ≤ 125°C (unless otherwise noted)
II33A Analog 3.3-V supply current Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled 6.3 mA
I33DIO Digital I/O 3.3-V core supply current All GPIO and communication pins are open 0.35 mA
I33D Digital I/O 3.3-V core supply current ROM program execution 60 mA
Flash programming in ROM mode 70 mA
I33 Total supply current Operating in ROM mode with all DPWMs enabled and switching at 2 MHz. DPWMs all unloaded. 105 mA
EAP – AGND –0.15 1.998 V
EAP – EAN –0.256 1.848 V
Typical error range AFE = 0 –256 248 mV
EAP – EAN Error voltage digital resolution AFE = 3 0.8 1 1.20 mV
AFE = 2 1.7 2 2.30
AFE = 1 3.55 4 4.45
AFE = 0 6.90 8 9.10
REA Input impedance (See Figure 4-3) AGND reference 0.5
IOFFSET Input offset current (See Figure 4-3) –5 5 μA
EADC offset Input voltage = 0 V at AFE = 0 –2 2 LSB
Input voltage = 0 V at AFE = 1 –2.5 2.5
Input voltage = 0 V at AFE = 2 –3 -3
Input voltage = 0 V at AFE = 3 –4 4
Sample rate 16 MHz
Analog front end amplifier bandwidth 100 MHz
A0 Gain See Figure 4-4 1 V/V
Minimum output voltage 30 mV
DAC range 0 1.6 V
VREF DAC reference resolution 10 bit, No dithering enabled 1.56 mV
VREF DAC reference resolution With 4 bit dithering enabled 97.6 μV
INL –3.0 3.0 LSB
DNL Does not include MSB transition –2.1 1.6 LSB
DNL at MSB transition –1.4 LSB
DAC reference voltage 1.58 1.61 V
τ Settling time From 10% to 90% 250 ns
IBIAS Bias current for PMBus address pins 9.5 10.5 μA
Measurement range for voltage monitoring 0 2.5 V
Internal ADC reference voltage 2.475 2.500 2.525 V
Change in Internal ADC reference from 25°C reference voltage(1) –40°C ≤ TA ≤ 25°C –1.2 mV
25°C ≤ TA ≤ 125°C –2.6
ADC12 INL integral nonlinearity, end point(9) (See Figure 5-1) ADC_SAMPLINGSEL = 0 to 6 for all ADC12 data –3.9 ±2 4.5 LSB
ADC12 INL integral nonlinearity, best fit(9) (See Figure 5-1) –2.3 ±1.5 2.6 LSB
ADC12 DNL differential nonlinearity(9) –0.8/+2.4 LSB
ADC Zero Scale Error –7 7 mV
ADC Full Scale Error –35 35 mV
Input bias VADC12 = 2.5 V 400 nA
Input leakage resistance(1) ADC_SAMPLINGSEL = 0 or ADC_SAMPLINGSEL = 6 1
Input Capacitance(1) 10 pF
ADC single sample conversion time(1) ADC_SAMPLINGSEL = 0 or ADC_SAMPLINGSEL = 6 3.9 μs
VOL Low-level output voltage(4) IOH = 4 mA, VV33DIO = 3 V DGND
+ 0.25
VOH High-level output voltage (4) IOH = –4 mA, VV33DIO = 3 V V33DIO – 0.6 V
VIH High-level input voltage VV33DIO = 3 V 2.1 V
VIL Low-level input voltage VV33DIO = 3 V 1.1 V
IOH Output sinking current 4 mA
IOL Output sourcing current –4 mA
TWD Watchdog time out range Total time is: TWD × (WDCTRL.PERIOD + 1) 14.6 17 20.5 ms
Time to disable DPWM output based on active FAULT pin signal High level on FAULT pin 70 ns
Processor master clock (MCLK) 31.25 MHz
tDelay Digital compensator delay(5) (1 clock = 32 ns) 6 clocks
t(reset) Pulse width needed at reset(1) 10 µs
Retention period of flash content (data retention and program) TJ = 25°C 100 years
Program time to erase one page or block in data flash or program flash 20 ms
Program time to write one word in data flash or program flash 20 µs
f(PCLK) Internal oscillator frequency –40°C to +125°C 240 250 260 MHz
–5°C to +85°C 245 250 255 MHz
Sync-in or sync-out pulse width SYNC pin 256 ns
Flash read 1 MCLKs
Flash rrite 20 μs
ISHARE Current share current source (See Figure 6-16) 238 259 μA
RSHARE Current share resistor (See Figure 6-16) 9.75 10.3
POWER ON RESET AND BROWN OUT (V33D pin, See Figure 5-2)
VGH Voltage good high 2.7 V
VGL Voltage good low 2.5 V
Vres Voltage at which IRESET signal is valid 0.8 V
tPOR Time delay after power is good or RESET relinquished 1 ms
Brownout Internal signal warning of brownout conditions 2.9 V
VTEMP Voltage range of sensor 1.46 2.44 V
Voltage resolution V/°C 5.9 mV/ºC
Temperature resolution °C per bit 0.1034 ºC/LSB
Accuracy(6)(7) –10 ±5 10 ºC
Temperature range –40 125 ºC
ITEMP Current draw of sensor when active 30 μA
tON Turn on time, settling time of sensor 100 μs
VAMB Ambient temperature Trimmed 25°C reading 1.85 V
DAC Reference DAC range 0 2.5 V
Reference voltage 2.478 2.5 2.513 V
Bits 7 bits
INL(6) –0.42 0.21 LSB
DNL(6) 0.06 0.12 LSB
Offset –5.5 19.5 mV
Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator.(1) 150 ns
Reference DAC buffered output load(8) 0.5 1 mA
Buffer offset (–0.5 mA) 0.3 V < VDAC < 2.17 V 0 10 mV
Buffer offset (1.0 mA) 0.3 V < VDAC < 2.17 V –10 0 mV
Specified by design. Not production tested.
DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
On the 40-pin package V33DIO is connected to V33D internally.
The maximum total current, IOH(max) and IOL(max) for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.
Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.
Specified by design. Not production tested.
Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
Available from reference DACs for comparators D, E, F, and G.
Minimum and maximum values are specified by design and characterization data.

PMBus/SMBus/I2C Timing

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in Section 4.6, Figure 4-1, and Figure 4-2. The values in Section 4.6 describe device functional during 400 kHz operating frequency. However, the device supports all three speeds, standard (100 kHz), fast (400 kHz). Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 100 400 kHz
fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 100 400 kHz
t(BUF) Bus free time between start and stop(1) 1.3 µs
t(HD:STA) Hold time after (repeated) start(1) 0.6 µs
t(SU:STA) Repeated start setup time(1) 0.6 µs
t(SU:STO) Stop setup time(1) 0.6 µs
t(HD:DAT) Data hold time Receive mode 0 ns
t(SU:DAT) Data setup time 100 ns
t(TIMEOUT) Error signal/detect(2) 35 ms
t(LOW) Clock low period 1.3 µs
t(HIGH) Clock high period(3) 0.6 µs
t(LOW:SEXT) Cumulative clock low slave extend time(4) 25 ms
tf Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) 20 + 0.1 Cb(5) 300 ns
tr Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) 20 + 0.1 Cb(5) 300 ns
Cb Total capacitance of one bus line 400 pF
Fast mode, 400 kHz
The device times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Cb (pF)
UCD3138A I2C_tim_dia_lusap2.gif Figure 4-1 I2C/SMBus/PMBus Timing Diagram
UCD3138A bus_timing_lusap2.gif Figure 4-2 Bus Timing in Extended Mode


Digital Power Peripherals (DPPs)

At the core of the UCD3138A controller are three DDPs. Each DPP can be configured to drive from one to eight DPWM outputs. Each DPP consists of:

  • Differential input error ADC (EADC) with sophisticated controls
  • Hardware accelerated digital 2-pole/2-zero PID based compensator
  • Digital PWM module with support for a variety of topologies

These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of supporting functions like input voltage feed forward, current mode control, and constant current/constant power, and so on. The simplest configuration is shown in the following figure:

UCD3138A fusion_dig_pwr_lusap2.gif

Front End

Figure 4-3 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable gain error amplifier, a high speed flash analog-to-digital converter (EADC), digital averaging filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of resolution on the EADC output. The output of the Front End module is a 9-bit sign extended result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In addition each EADC has the ability to automatically select the AFE value such that the minimum resolution is maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the digital compensator for processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, and so on. Some additional features include the ability to change the polarity of the error measurement and an absolute value mode which automatically adds the DAC value to the error.

It is possible to operate the controller in a peak current mode control configuration; an EADC is recommended for implementing peak current mode control. In this mode, topologies like a phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified in Section 4.5.

UCD3138A front-end-diff-amp.gif Figure 4-3 Input Stage of EADC Module
UCD3138A EADC_2_mod2_lusc66.gif Figure 4-4 Front End Module
(Front End 2 Recommended for Peak Current Mode Control)

DPWM Module

The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple DPWM modules within the UCD3138A system can be configured to support all key power topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM configurations.

The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width modulated outputs for the power stage switches. The compensator calculates the duty ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON time is 250 psec.

Each DPWM module can be synchronized to another module or to an external sync signal. An input SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of the DPWM outputs for multiple power stages can be tightly controlled.

The DPWM logic is probably the most complex of the Digital Peripherals. It receives the output of the compensator and converts it into the correct DPWM output for several power supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault handling is covered in the Fault Mux section.

Each DPWM module supports the following features:

  • Dedicated 14 bit time-base with period and frequency control
  • Shadow period register for end of period updates.
  • Quad-event control registers (A and B, rising and falling) (Events 1 to 4)
    • Used for on/off DPWM duty ratio updates.
  • Phase control relative to other DPWM modules
  • Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
  • Support for two independent edge placement DPWM outputs (same frequency or period setting)
  • Dead-time between DPWM A and B outputs
  • High Resolution capabilities – 250 ps
  • Pulse cycle adjustment of up to ±8.192 µs (32768 × 250 ps)
  • Active high/ active low output polarity selection
  • Provides events to trigger both CPU interruptions and start of ADC12 conversions.

DPWM Events

Each DPWM can control the following timing events:

  1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship to the DPWM period. The programmed value set in the register should be one fourth of the value calculated based on the DPWM clock. The clock controlling the circuitry runs at one fourth of the DPWM clock (PCLK = 250 MHz max). When this sample trigger count is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a CLA calculation, and a DPWM update. Oversampling can be set for 2, 4, or 8 times the sampling rate.
  2. Phase Trigger Count – count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
  3. Period – low resolution switching period count. (count of PCLK cycles)
  4. Event 1 – count offset for rising DPWM A event. (PCLK cycles)
  5. Event 2 – DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
  6. Event 3 – DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
  7. Event 4 – DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
  8. Cycle Adjust – Constant offset for Event 2 and Event 4 adjustments.

Basic comparisons between the programmed registers and the DPWM counter can create the desired edge placements in the DPWM. High resolution edge capability is available on Events 2, 3, and 4.

Figure 4-5 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own registers, not by the filter output. In other words, the power supply control loop is not closed.

The Sample Trigger signals are used to trigger the front end to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off.

UCD3138A mulit2_opn_loop_lusc66.gif
Events which change with DPWM mode:
  • DPWM A Rising Edge = Event 1
  • DPWM A Falling Edge = Event 2 + Cycle Adjust A
  • DPWM B Rising Edge = Event 3
  • DPWM B Falling Edge = Event 4 + Cycle Adjust B
  • Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:
  • Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
  • Begin, Blanking B End
Figure 4-5 Multi Mode Open Loop

High Resolution DPWM

Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM edges, the UCD3138A DPWM can generate waveforms with resolutions as small as 250 ps. This is 16× the resolution of the clock driving the DPWM module.

This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz. The high resolution section of DPWM can be enabled or disabled, and the resolution can be defined in several steps between 4 ns to 250 ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN and HIRES_SCALE inside the DPWM Control register 1. See the Power Peripherals programmer’s manual for details.


The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the error voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The 01 setting triggers 2X oversampling, the 10 setting triggers 4X over sampling, and the 11 triggers oversampling at 8X.

DPWM Interrupt Generation

The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence synchronization. Table 4-1 outlines the divide ratios that can be programmed.

DPWM Interrupt Scaling/Range

Table 4-1 DPWM Interrupt Divide Ratio

Interrupt Divide Setting Interrupt Divide Count Interrupt Divide Count (hex) Switching Period Frames (Assume 1-MHz Loop) Number of 32-MHz Processor Cycles
1 0 00 1 32
2 1 01 2 64
3 3 03 4 128
4 7 07 8 256
5 15 0F 16 512
6 31 1F 32 1024
7 47 2F 48 1536
8 63 3F 64 2048
9 79 4F 80 2560
10 95 5F 96 3072
11 127 7F 128 4096
12 159 9F 160 5120
13 191 BF 192 6144
14 223 DF 224 7168
15 255 FF 256 8192

DPWM Synchronization

This section describes the register settings and hardware considerations necessary to modulate the DPWM pins with PCMC and internal slope compensation.

DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to DPWM2, ½ period out of phase using these commands:

Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave
Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave
Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave
LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0;
LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 1;
LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2;
// Slave to dpwm-0
// Slave to dpwm-1
// Slave to dpwm-2

If the event registers on the DPWMs are the same, the two pairs of signals are symmetrical. All code examples are taken from the PSFB EVM code, unless otherwise stated.

Synchronous Rectifier Dead-Time Optimization Peripheral

The UCD3138A has an advanced dead time control interface where it can accept output signals from the UCD7138 device and optimize SR gate driver signals accordingly. The UCD7138 low-side MOSFET driver is a high-performance driver for secondary-side synchronous rectification (SR) with body diode conduction sensing. The device is suitable for high power high efficiency isolated converter applications where dead-time optimization is desired. The UCD7138 gate driver is a companion device to the UCD3138A highly-integrated digital controller for isolated power.

UCD3138A front-page-simplified-application_slusc66.gif Figure 4-6 Synchronous Rectifier Peripheral use with Synchronous Rectifier Driver

DTC0 and DTC1 are received body diode conduction inputs from UCD7138. SR0_DPWM and SR1_DPWM are the DPWM waveforms for the SRs. The red and green edges are moving edges controlled by both the filter output and the DTC interface. In each cycle, right after the falling edge of the SR DPWM waveform, a body diode conduction time detection window is generated. The detection window is defined by both DETECT_BLANK and DETECT_LEN registers. During this detection window, a 4-ns timer capture counts how long the body diode conducts. Then the DPWM turn off edge of the next cycle is adjusted accordingly.

UCD3138A diode_const_timing_slusc66.gif Figure 4-7 Timing Diagram of the DTC Interface

Figure 4-8 shows how the turn off edge is adjusted based on the DTC measurement of the previous cycle. The A_ADJ and B_ADJ registers in DTCMONITOR are signed accumulators; default value is 0.

UCD3138A DTC_interface_principle_slusc66.gif Figure 4-8 DTC Interface Principle

Based on the DTC measured, in the next cycle:

  • A_ADJ = A_ADJ + A_∆
  • A_ADJ = A_ADJ + B_∆

In each cycle, the A_ADJ and B_ADJ accumulator values are dynamically adjust the dead time. The ∆ value changes after the measured body diode conduction time. A_ADJ and B_ADJ have been measured and compared to the threshold values in automatic control mode. A_ADJ and B_ADJ can be controlled by firmware while in manual control mode.

Other figures of this peripheral include negative current fault protection, consecutive fault counter, DTC input multiplexor, etc. For details, refer to the programmer's manual.

Typical Temperature Characteristics

UCD3138A G005a_SLUSAP2.gif Figure 4-9 EADC LSB Size With 4X Gain (mV) vs Temperature
UCD3138A G006b_SLUSAP2.gif Figure 4-11 ADC12 Measurement Temperature Sensor Voltage vs Temperature
UCD3138A G002b_SLUSAP2.gif Figure 4-13 ADC12 Temperature Sensor Measurement Error vs Temperature
UCD3138A C001_SLUSAP2.png Figure 4-10 BP18 Voltage vs Temperature
UCD3138A G003b_SLUSAP2.gif Figure 4-12 ADC12 2.5-V Reference vs Temperature
UCD3138A G004b_SLUSAP2.gif Figure 4-14 Oscillator Frequency (2-MHz Reference, Divided Down from 250 MHz) vs Temperature