SLVSC86A January   2014  – March 2014 UCD9244-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Terminal Configuration and Functions
    1.     Terminal Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics (Continued)
    7. 7.7  ADC Monitoring Intervals And Response Times
    8. 7.8  Hardware Fault Detection Latency
    9. 7.9  PMBus/SMBus/I2C
    10. 7.10 I2C/SMBus/PMBus Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PMBus Interface
      2. 8.3.2  Resistor Programmed PMBus Address Decode
      3. 8.3.3  VID Interface
      4. 8.3.4  Jtag Interface
      5. 8.3.5  Bias Supply Generator (Shunt Regulator Controller)
      6. 8.3.6  Power-On Reset
      7. 8.3.7  External Reset
      8. 8.3.8  ON_OFF_CONFIG
      9. 8.3.9  Output Voltage Adjustment
      10. 8.3.10 Calibration
      11. 8.3.11 Analog Front End (AFE)
      12. 8.3.12 Voltage Sense Filtering
      13. 8.3.13 DPWM Engine
      14. 8.3.14 Rail/Power Stage Configuration
      15. 8.3.15 DPWM Phase Synchronization
      16. 8.3.16 Output Current Measurement
      17. 8.3.17 Current Sense Input Filtering
      18. 8.3.18 Over-Current Detection
      19. 8.3.19 Input Voltage Monitoring
      20. 8.3.20 Input UV Lockout
      21. 8.3.21 Temperature Monitoring
      22. 8.3.22 Auxiliary ADC Input Monitoring
      23. 8.3.23 Soft Start, Soft Stop Ramp Sequence
      24. 8.3.24 Non-Volatile Memory Error Correction Coding
      25. 8.3.25 Data Logging
    4. 8.4 Device Functional Modes
      1. 8.4.1 4-Bit VID Mode
      2. 8.4.2 6-Bit VID Mode
      3. 8.4.3 8-Bit VID Mode
      4. 8.4.4 Current Foldback Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Automatic System Identification (Auto-ID)
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Digital Compensator
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics (Continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
DIGITAL INPUTS/OUTPUTS
VOL Low-level output voltage IOL = 6 mA(1), V33DIO = 3 V Dgnd +0.3 V
VOH High-level output voltage IOH = -6 mA(2), V33DIO = 3 V V33DIO
–0.6V		 V
VIH High-level input voltage V33DIO = 3V 2.1 3.6 V
VIL Low-level input voltage V33DIO = 3.5 V 1.4 V
SYSTEM PERFORMANCE
VRESET Voltage where device comes out of reset V33D terminal 2.3 2.4 V
tRESET Pulse width needed for reset nRESET terminal 2 µs
VRefAcc Setpoint Reference Accuracy Vref commanded to be 1V, at 25°C AFEgain = 4,
1V input to EAP/N measured at output of the EADC(3)		 –10 10 mV
Setpoint Reference Accuracy over temperature –55°C to 125°C –40 40 mV
VDiffOffset Differential offset between gain settings AFEgain = 4 compared to
AFEgain = 1, 2, or 8		 –4 4 mV
tDelay Digital Compensator Delay 240 240 + 1 switching cycle ns
FSW Switching Frequency 15.260 2000 kHz
Accuracy –5% 5%
Duty Max and Min Duty Cycle 0% 100%
V33Slew Minimum V33 slew rate V33 slew rate between 2.3V and 2.9V,
TJ = -40°C to 125°C		 0.25 V/ms
tretention Retention of configuration parameters(6) TJ = 25 °C 100 Years
Write_Cycles Number of nonvolatile erase/write cycles TJ = 25 °C 20 K cycles
RateVID Max VID message rate All rails configured to accept VID messages(5) 1 msg/msec
All rails configured to accept 6-bit VID messages(5) 4
All rails configured to accept 8-bit VID messages(4) 4
(1) The maximum IOL, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
(2) The maximum IOH, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
(3) With default device calibration. PMBus calibration can be used to improve the regulation tolerance.
(4) VID message rate on PMBus interface.
(5) VID message rate on each interface. Measured over a 1.0 msec interval.
(6) The data retention specification is based on accelerated stress testing at 170°C for 420 hours and using an Arrhenius model with activation energy of 0.6 eV.