Refer to the PDF data sheet for device specific package drawings
The correct power-up and shut-down sequences must be followed to avoid damage to the device.
While VBAT or VIO or both are deasserted, no signals should be driven to the device. The only exception is the slow clock that is a fail-safe I/O.
While VBAT, VIO, and slow clock are fed to the device, but WL_EN is deasserted (low), the device is in SHUTDOWN state. In SHUTDOWN state all functional blocks, internal DC-DCs, clocks, and LDOs are disabled.
To perform the correct power-up sequence, assert (high) WL_EN. The internal DC-DCs, LDOs, and clock start to ramp and stabilize. Stable slow clock, VIO, and VBAT are prerequisites to the assertion of one of the enable signals.
To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device (VBAT, VIO, and slow clock) are still stable and available. The supplies to the chip (VBAT and VIO) can be deasserted only after both enable signals are deasserted (low).
Figure 8-2 shows the general power scheme for the module, including the power-down sequence.