JAJSM24A December   2023  – May 2024 ADC3910D125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 5.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 5.10 Timing Requirements
    11. 5.11 Output Interface Timing Diagram
    12. 5.12 Typical Characteristics - 25MSPS
    13. 5.13 Typical Characteristics - 65MSPS
    14. 5.14 Typical Characteristics - 125MSPS
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ADC Features
        1. 6.3.1.1 Low Latency Mode
        2. 6.3.1.2 Full Digital Feature Mode
        3. 6.3.1.3 Interleaving Mode
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Single Ended Input
        2. 6.3.2.2 Differential Input
        3. 6.3.2.3 Analog Input Bandwidth
      3. 6.3.3 Sampling Clock Input
      4. 6.3.4 Voltage Reference
      5. 6.3.5 Over-range (OVR)
      6. 6.3.6 Digital Features
        1. 6.3.6.1 Digital Down Converter
          1. 6.3.6.1.1 Digital Down Converter Data Select
          2. 6.3.6.1.2 Decimation Filter
          3. 6.3.6.1.3 DDC Over-range
          4. 6.3.6.1.4 Output Formatting with Decimation
        2. 6.3.6.2 Digital Comparator
          1. 6.3.6.2.1 Comparator Data Select
          2. 6.3.6.2.2 Comparator High and Low Threshold
          3. 6.3.6.2.3 Comparator Configuration Compare Mode
          4. 6.3.6.2.4 Comparator Event Configuration
        3. 6.3.6.3 Statistics Engine
          1. 6.3.6.3.1 Statistics Engine Data Select
          2. 6.3.6.3.2 Window Configuration
        4. 6.3.6.4 Digital Alerts
      7. 6.3.7 Digital Interface
        1. 6.3.7.1 Parallel CMOS Output
        2. 6.3.7.2 Serialized CMOS Output
      8. 6.3.8 Test Patterns
        1. 6.3.8.1 Bypass Test Pattern
        2. 6.3.8.2 Digital Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Power Down Options
    5. 6.5 Programming
      1. 6.5.1 Configuration using the SPI interface
        1. 6.5.1.1 Register Write
        2. 6.5.1.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 Statistics Engine Register Map
      3. 6.6.3 Alerts Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Sampling Clock
        3. 7.2.2.3 Voltage Reference
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Register Initialization During Operation
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
6.3.6.1.4 Output Formatting with Decimation

In serial CMOS mode, the ADC3910Dx および ADC3910Sx has a configurable output data mapping. Default bit size in serial CMOS is 10 bits wide and interface default is set to DDR. Interface options are double data rate (DDR), half double data rate (HDDR), and single data rate (SDR) via SPI write to register 0x098.

By default DDR mode clocks output data by alternating channel A data on the rising and channel B data on the falling edge of DCLK on the same lane. This behavior can be changed to clock all of channel A data first and then channel B data via SPI write to DDR_MODE (0x0A6). HDDR mode clocks channel A data on separate output lanes from channel B data via SPI write to HDDR_EN (0x098).

SDR mode clocks data only on rising edge; therefore, to clock both data samples in a cycle, requires double the data clock speed. The following diagrams show the different available configurations that can be programmed, and Table 6-4 shows actual data and clock rates.

Table 6-3 Serial CMOS Lane Rate Examples with Real Decimation and 12/16-bit Output Resolution
Output Resolution Decimation Lanes Serialization DCLK DCLK Divider FCLK
Register 0xA7 Register 0x200 Registers 0xAE...B3 Register 0xA6 Register 0xA8 Register 0x88
8 bits Bypass 8 1 FS /1 N/A
10 bits 10 1 FS /1 N/A
12 bits 12 1 FS /1 N/A
/2 12 1 FS / 2 /2 N/A
/4 12 1 FS / 4 /4 N/A
/8 12 1 FS / 8 /8 N/A
/16 12 1 FS /16 /16 N/A
16 bits /2 8 2 FS /2 FS / 2
/4 8 2 FS / 2 /4 FS / 2
4 4 FS FS / 4
/8 8 2 FS / 4 /8 FS / 2
4 4 FS / 2 FS / 4
2 8 FS FS / 8
/16 8 2 FS / 8 /16 FS / 2
4 4 FS / 4 FS / 4
2 8 FS / 2 FS / 8
Note: 16 bit resolution does not support a serialization factor of 1.
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 16 Bit, 8 Lanes, 2x SerializationFigure 6-21 16 Bit, 8 Lanes, 2x Serialization
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 16 Bit, 4 Lanes, 4x SerializationFigure 6-22 16 Bit, 4 Lanes, 4x Serialization
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 16 Bit, 2 Lanes, 8x SerializationFigure 6-23 16 Bit, 2 Lanes, 8x Serialization