JAJSM24A December   2023  – May 2024 ADC3910D125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 5.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 5.10 Timing Requirements
    11. 5.11 Output Interface Timing Diagram
    12. 5.12 Typical Characteristics - 25MSPS
    13. 5.13 Typical Characteristics - 65MSPS
    14. 5.14 Typical Characteristics - 125MSPS
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ADC Features
        1. 6.3.1.1 Low Latency Mode
        2. 6.3.1.2 Full Digital Feature Mode
        3. 6.3.1.3 Interleaving Mode
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Single Ended Input
        2. 6.3.2.2 Differential Input
        3. 6.3.2.3 Analog Input Bandwidth
      3. 6.3.3 Sampling Clock Input
      4. 6.3.4 Voltage Reference
      5. 6.3.5 Over-range (OVR)
      6. 6.3.6 Digital Features
        1. 6.3.6.1 Digital Down Converter
          1. 6.3.6.1.1 Digital Down Converter Data Select
          2. 6.3.6.1.2 Decimation Filter
          3. 6.3.6.1.3 DDC Over-range
          4. 6.3.6.1.4 Output Formatting with Decimation
        2. 6.3.6.2 Digital Comparator
          1. 6.3.6.2.1 Comparator Data Select
          2. 6.3.6.2.2 Comparator High and Low Threshold
          3. 6.3.6.2.3 Comparator Configuration Compare Mode
          4. 6.3.6.2.4 Comparator Event Configuration
        3. 6.3.6.3 Statistics Engine
          1. 6.3.6.3.1 Statistics Engine Data Select
          2. 6.3.6.3.2 Window Configuration
        4. 6.3.6.4 Digital Alerts
      7. 6.3.7 Digital Interface
        1. 6.3.7.1 Parallel CMOS Output
        2. 6.3.7.2 Serialized CMOS Output
      8. 6.3.8 Test Patterns
        1. 6.3.8.1 Bypass Test Pattern
        2. 6.3.8.2 Digital Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Power Down Options
    5. 6.5 Programming
      1. 6.5.1 Configuration using the SPI interface
        1. 6.5.1.1 Register Write
        2. 6.5.1.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 Statistics Engine Register Map
      3. 6.6.3 Alerts Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Sampling Clock
        3. 7.2.2.3 Voltage Reference
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Register Initialization During Operation
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
6.3.6.1.2 Decimation Filter

The ADC3910Dx および ADC3910Sx has a stop band rejection of at least 70dB, and a pass-band bandwidth of approximately 80%. Table 6-2 gives an overview of the pass-band bandwidth of the different decimation settings with respect to ADC sampling rate FS.

Table 6-2 Decimation Filter Summary and Maximum Available Output Bandwidth
REAL DECIMATION DECIMATION SETTING (N) OUTPUT RATE OUTPUT BANDWIDTH OUTPUT RATE
(FS = 125MSPS)		 OUTPUT BANDWIDTH
(FS = 125MSPS)
Real 2 FS / 2 0.8 × FS / (2 × 2) 62.5MSPS 25MHz
4 FS / 4 0.8 × FS / (4 × 2) 31.25MSPS 12.5MHz
8 FS / 8 0.8 × FS / (8 × 2) 15.625MSPS 6.25MHz
16 FS / 16 0.8 × FS / (16 × 2) 7.8125MSPS 3.125MHz

The decimation filter responses are normalized to the ADC sampling clock frequency FS and illustrated in Figure 6-12 to Figure 6-19. They are interpreted as follows:

Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 6-11. The x-axis shows the offset frequency normalized to the ADC sampling rate FS.

For example, in the divide-by-4 setup, the output data rate is FS / 4 with a Nyquist zone of FS / 8 or 0.125 × FS. The transition band (colored in blue) is centered around 0.125 × FS and the alias transition band is centered at 0.375 × FS. The stop-bands (colored in red), which alias on top of the pass-band, are centered at 0.25 × FS and 0.5 × FS.

ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Interpretation of the Decimation Filter Plots Figure 6-11 Interpretation of the Decimation Filter Plots
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Decimation by 2 frequency responseFigure 6-12 Decimation by 2 frequency response
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Decimation by 4 frequency responseFigure 6-14 Decimation by 4 frequency response
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Decimation by 8 frequency responseFigure 6-16 Decimation by 8 frequency response
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Decimation by 16 frequency responseFigure 6-18 Decimation by 16 frequency response
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 SNR Performance vs Decimation Mode
FIN = 1 MHz, AIN = -1dBFS, 16-bit resolution mode
Figure 6-20 SNR Performance vs Decimation Mode
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Decimation by 2 passband ripple responseFigure 6-13 Decimation by 2 passband ripple response
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Decimation by 4 passband ripple responseFigure 6-15 Decimation by 4 passband ripple response
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Decimation by 8 passband ripple responseFigure 6-17 Decimation by 8 passband ripple response
ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 Decimation by 16 passband ripple responseFigure 6-19 Decimation by 16 passband ripple response