JAJSM24A December   2023  – May 2024 ADC3910D125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 5.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 5.10 Timing Requirements
    11. 5.11 Output Interface Timing Diagram
    12. 5.12 Typical Characteristics - 25MSPS
    13. 5.13 Typical Characteristics - 65MSPS
    14. 5.14 Typical Characteristics - 125MSPS
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ADC Features
        1. 6.3.1.1 Low Latency Mode
        2. 6.3.1.2 Full Digital Feature Mode
        3. 6.3.1.3 Interleaving Mode
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Single Ended Input
        2. 6.3.2.2 Differential Input
        3. 6.3.2.3 Analog Input Bandwidth
      3. 6.3.3 Sampling Clock Input
      4. 6.3.4 Voltage Reference
      5. 6.3.5 Over-range (OVR)
      6. 6.3.6 Digital Features
        1. 6.3.6.1 Digital Down Converter
          1. 6.3.6.1.1 Digital Down Converter Data Select
          2. 6.3.6.1.2 Decimation Filter
          3. 6.3.6.1.3 DDC Over-range
          4. 6.3.6.1.4 Output Formatting with Decimation
        2. 6.3.6.2 Digital Comparator
          1. 6.3.6.2.1 Comparator Data Select
          2. 6.3.6.2.2 Comparator High and Low Threshold
          3. 6.3.6.2.3 Comparator Configuration Compare Mode
          4. 6.3.6.2.4 Comparator Event Configuration
        3. 6.3.6.3 Statistics Engine
          1. 6.3.6.3.1 Statistics Engine Data Select
          2. 6.3.6.3.2 Window Configuration
        4. 6.3.6.4 Digital Alerts
      7. 6.3.7 Digital Interface
        1. 6.3.7.1 Parallel CMOS Output
        2. 6.3.7.2 Serialized CMOS Output
      8. 6.3.8 Test Patterns
        1. 6.3.8.1 Bypass Test Pattern
        2. 6.3.8.2 Digital Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Power Down Options
    5. 6.5 Programming
      1. 6.5.1 Configuration using the SPI interface
        1. 6.5.1.1 Register Write
        2. 6.5.1.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 Statistics Engine Register Map
      3. 6.6.3 Alerts Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Sampling Clock
        3. 7.2.2.3 Voltage Reference
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Register Initialization During Operation
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

6.6.3 Alerts Register Map

Table 6-251 ALERT Registers
Address Register Name
1AFh ALERT_PULSE_WIDTH
1B4h ALERT_INVERT_7:0
1B5h ALERT_INVERT_15:8
1B6h ALERT_INVERT_18:16
1C0h ALERT_TRIG_7:0
1C1h ALERT_TRIG_15:8
1C2h ALERT_TRIG_18:16
1CCh ALERT_STICKY_7:0
1CDh ALERT_STICKY_15:8
1CEh ALERT_STICKY_18:16
1D8h ALERT_STICKY_CLR_7:0
1D9h ALERT_STICKY_CLR_15:8
1DAh ALERT_STICKY_CLR_18:16
1E4h ALERT_CNT_7:0
1E5h ALERT_CNT_15:8
1EAh ALERT_CNT
1ECh ALERT_THRESHOLD_7:0
1EDh ALERT_THRESHOLD_15:8

6.6.3.1 0x1AF Register (Address = 1AFh) [Reset = 00h]

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Table 6-252 0x1AF Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_PULSE_WIDTH R/W 0h ALERT pulse width = 2ALERTPULSE WIDTH + 1 CLK cycles. Minimum width is 1 CLK cycle.

6.6.3.2 0x1B4 Register (Address = 1B4h) [Reset = 00h]

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Table 6-253 0x1B4 Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_INVERT__7:0 R/W 0h Invert signals routed to ALERT pin. This register is a mask so multiple signals can be inverted simultaneously by enabling the corresponding bit. Bit 0: Equal to THRESHOLD HI CHA Bit 1: Greater than THRESHOLD HI CHA Bit 2: Less than THRESHOLD LO CHA Bit 3: All ones Bit 4: All zeros Bit 5: Less than THRESHOLD HI CHA Bit 6: Greater than THRESHOLD LO CHA Bit 7: Equal to THRESHOLD HI CHB Bit 8: Greater than THRESHOLD HI CHB Bit 9: Less than THRESHOLD LO CHB Bit 10: All ones Bit 11: All zeros Bit 12: Less than THRESHOLD HI CHB Bit 13: Greater than THRESHOLD LO CHB Bit 14: ADC channel A overrange Bit 15: ADC channel B overrange Bit 16: Statistics engine window complete

6.6.3.3 0x1B5 Register (Address = 1B5h) [Reset = 00h]

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Table 6-254 0x1B5 Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_INVERT__15:8 R/W 0h Invert signals routed to ALERT pin. This register is a mask so multiple signals can be inverted simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask. See register 0x1B4 for bit mask.

6.6.3.4 0x1B6 Register (Address = 1B6h) [Reset = 0h]

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Table 6-255 0x1B6 Register Field Descriptions
Bit Field Type Reset Description
2:0 ALERT_INVERT__18:16 R/W 0h Invert signals routed to ALERT pin. This register is a mask so multiple signals can be inverted simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.5 0x1C0 Register (Address = 1C0h) [Reset = 00h]

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Table 6-256 0x1C0 Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_TRIG__7:0 R/W 0h Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.6 0x1C1 Register (Address = 1C1h) [Reset = 00h]

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Table 6-257 0x1C1 Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_TRIG__15:8 R/W 0h Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.7 0x1C2 Register (Address = 1C2h) [Reset = 0h]

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Table 6-258 0x1C2 Register Field Descriptions
Bit Field Type Reset Description
0 ALERT_TRIG__18:16 R/W 0h Signals set as triggers for ALERT pin. This register is a mask so multiple signals can be triggered simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.8 0x1CC Register (Address = 1CCh) [Reset = 00h]

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Table 6-259 0x1CC Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_STICKY__7:0 R/W 0h Signals set as sticky for ALERT pin, that is, once triggered remains triggered until cleared in ALERT STICKY CLR MASK. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.9 0x1CD Register (Address = 1CDh) [Reset = 00h]

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Table 6-260 0x1CD Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_STICKY__15:8 R/W 0h Signals set as sticky for ALERT pin, that is, once triggered remains triggered until cleared in ALERT STICKY CLR MASK. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.10 0x1CE Register (Address = 1CEh) [Reset = 0h]

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Table 6-261 0x1CE Register Field Descriptions
Bit Field Type Reset Description
0 ALERT_STICKY__18:16 R/W 0h Signals set as sticky for ALERT pin, that is, once triggered remains triggered until cleared in ALERT STICKY CLR MASK. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.11 0x1D8 Register (Address = 1D8h) [Reset = 00h]

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Table 6-262 0x1D8 Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_STICKY_CLR__7:0 R/W 0h Signals set as sticky for ALERT pin. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.12 0x1D9 Register (Address = 1D9h) [Reset = 00h]

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Table 6-263 0x1D9 Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_STICKY_CLR__15:8 R/W 0h Signals set as sticky for ALERT pin. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.13 0x1DA Register (Address = 1DAh) [Reset = 0h]

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Table 6-264 0x1DA Register Field Descriptions
Bit Field Type Reset Description
0 ALERT_STICKY_CLR__18:16 R/W 0h Signals set as sticky for ALERT pin. This register is a mask so multiple signals can be set as sticky simultaneously by enabling the corresponding bit. See register 0x1B4 for bit mask.

6.6.3.14 0x1E4 Register (Address = 1E4h) [Reset = 00h]

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Table 6-265 0x1E4 Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_CNT__7:0 R/W 0h Counter of the input alerts cross the threshold before the output alert is triggered

6.6.3.15 0x1E5 Register (Address = 1E5h) [Reset = 00h]

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Table 6-266 0x1E5 Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_CNT__15:8 R/W 0h Counter of the input alerts cross the threshold before the output alert is triggered

6.6.3.16 0x1EA Register (Address = 1EAh) [Reset = 00h]

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Table 6-267 0x1EA Register Field Descriptions
Bit Field Type Reset Description
7 CNT_MODE_B R/W 0h Sets the ALERT count mode for channel B
0b = Level-based count
1b = Rise-based count
6 CNT_MODE_A R/W 0h Sets the ALERT count mode for channel A
0b = Level-based count
1b = Rise-based count
5:1 RESERVED R 0h
0 CNT_EN R/W 0h Enables alert window mode. In this mode alert is triggered when input triggers cross (alert_thres) number of time in alert_cnt window
0b = Disable alert window mode
1b = Enable alert window mode

6.6.3.17 0x1EC Register (Address = 1ECh) [Reset = 00h]

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Table 6-268 0x1EC Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_THRESHOLD__7:0 R/W 0h Sets the threshold the count of input alerts must cross before the output alert is triggered

6.6.3.18 0x1ED Register (Address = 1EDh) [Reset = 00h]

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Table 6-269 0x1ED Register Field Descriptions
Bit Field Type Reset Description
7:0 ALERT_THRESHOLD__15:8 R/W 0h Sets the threshold the count of input alerts must cross before the output alert is triggered