JAJSM24 データシート

JAJSM24A December 2023 – May 2024 ADC3910D125

PRODUCTION DATA

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メカニカル・データ（パッケージ｜ピン）

RSM|32
- MPQF195B

サーマルパッド・メカニカル・データ

6.6.1 Register Descriptions

Table 6-5 DEVICE Registers

Address	Register Name
0h	RESET
38h	CFG_ALERT
39h	SPARE_REG
84h	INTERLEAVE
85h	REF_EQ
88h	DEV_CFG_1
89h	DEV_CFG_2
8Ah	CLK_CFG_1
8Bh	CLK_CFG_2
8Ch	PDN_CFG
8Dh	DEV_CFG_3
8Eh	CLK_CFG_3
8Fh	CLK_CFG_4
90h	PIN_CFG_1
91h	TEST_PAT_CFG
91h	TEST_PATTERN_CFG
92h	TEST_PATTERN_CHB_7:0
93h	TEST_PATTERN_CHB_13:8
94h	TEST_PATTERN_CHA_7:0
95h	TEST_PATTERN_CHA_13:8
97h	GLOBAL_PDN
98h	INTERFACE_CFG_1
9Ch	INTERFACE_CFG_2
9Eh	HFSB_FPDN_CFG
A0h	INTERFACE_CFG_3
A1h	DIG_PATTERN_EN
A2h	DIG_PATTERN_CHA_7:0
A3h	DIG_PATTERN_CHA_15:8
A4h	DIG_PATTERN_CHB_7:0
A5h	DIG_PATTERN_CHB_15:8
A6h	INTERFACE_CFG_4
A7h	OUTPUT_DATA_WIDTH
A8h	DCLK_DIVIDER
AEh	OUTPUT_BIT_MAPPER_D0_D1
AFh	OUTPUT_BIT_MAPPER_D2_D3
B0h	OUTPUT_BIT_MAPPER_D4_D5
B1h	OUTPUT_BIT_MAPPER_D6_D7
B2h	OUTPUT_BIT_MAPPER_D8_D9
B3h	OUTPUT_BIT_MAPPER_D10_D11
B6h	ROUND
C8h	COMP_THRESHOLD_HI_CHA_7:0
C9h	COMP_THRESHOLD_HI_CHA_11:8
CAh	COMP_THRESHOLD_HI_CHB_7:0
CBh	COMP_THRESHOLD_HI_CHB_11:8
CCh	COMP_THRESHOLD_LO_CHA_7:0
CDh	COMP_THRESHOLD_LO_CHA_11:8
CEh	COMP_THRESHOLD_LO_CHB_7:0
CFh	COMP_THRESHOLD_LO_CHB_11:8
D0h	COMP_HYSTERESIS_CHA_7:0
D1h	COMP_HYSTERESIS_CHA_11:8
D2h	COMP_HYSTERISIS_CHB_7:0
D3h	COMP_HYSTERISIS_CHB_11:8
D3h	COMP_SLEW
D4h	DECIMATION
D5h	PROG_GAIN_CHA
D6h	PROG_GAIN_CHB
D8h	IL_GAIN_CHA_7:0
D9h	IL_GAIN_CHA_15:8
DAh	IL_GAIN_CHB_7:0
DBh	IL_GAIN_CHB_15:8
DCh	OFFSET_CHA_7:0
DDh	OFFSET_CHA_15:8
DEh	OFFSET_CHB_7:0
DFh	OFFSET_CHB_15:8
E0h	CH_CORR_EN
200h	DDC_CFG_1
201h	STATS_COMP_DATA_SEL
202h	OUTPUT_DATA_SEL
203h	COMP_DDC_DATA_SEL
204h	OUTPUT_STATS_DATA_SEL
205h	OVR_CHB
206h	OVR_CHA
304h	CLK_TIM_ADJ_CHA
305h	CLK_TIM_ADJ_CHB
306h	DCLK_DLL_PD
307h	DIG_INPUT_CFG
309h	BUF_VCM_CURR
30Ah	BUF_CURR
30Bh	DEV_CFG_4
484h	GBL_CLK_CFG_1
4BEh	GBL_CLK_CFG_2
4BFh	GBL_CLK_CFG_3

Complex bit access types are encoded to fit into small table cells. Table 6-6 shows the codes that are used for access types in this section.

Table 6-6 Device Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

6.6.1.1 RESET Register (Address = 0h) [Reset = 00h]

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Table 6-7 RESET Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESET	W	0h	This bit resets all internal registers to the default values and self clears to 0.
6:0	RESERVED	R	0h

6.6.1.2 CFG_ALERT Register (Address = 38h) [Reset = 0h]

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Table 6-8 CFG_ALERT Register Field Descriptions

Bit	Field	Type	Reset	Description
0	CFG_ALERT	R	0h	Indicates that the device is ready to be configured. The user can poll this bit before starting the device configuration. Alternatively, the user can wait for a fixed time (2000 clock cycles) after reset release before triggering device configuration

6.6.1.3 SPARE_REG Register (Address = 39h) [Reset = 00h]

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Table 6-9 SPARE_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	SPARE_REG	R/W	0h	This field has no functionality and can be used for validating SPI writes.

6.6.1.4 INTERLEAVE Register (Address = 84h) [Reset = 0h]

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Table 6-10 INTERLEAVE Register Field Descriptions

Bit	Field	Type	Reset	Description
2	INTERLEAVE	R/W	0h	Enables interleaving mode where channels A and B are both sampling channel A input and channel B clock is 180 degrees out of phase with respect to channel A to achieve a 2x sampling rate. Only applies to dual channel devices. 0b = Interleaving mode disabled 1b = Interleaving mode enabled
1:0	RESERVED	R	0h

6.6.1.5 REF_EQ Register (Address = 85h) [Reset = 00h]

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Table 6-11 REF_EQ Register Field Descriptions

Bit	Field	Type	Reset	Description
6	REF_EQ	R/W	0h	Enable when using external reference to improve temperature tracking. Internal bandgap is expected to have 7 mV of variation across the device operating temperature. 0b = Reference equalization disabled 1b = Reference equalization enabled
5:0	RESERVED	R	0h

6.6.1.6 CLK_RESET Register (Address = 87h) [Reset = 00h]

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Table 6-12 CLK_RESET Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5:0	RESERVED	R	0h

6.6.1.7 DEV_CFG_1 Register (Address = 88h) [Reset = 00h]

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Table 6-13 DEV_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FCLK_EN	R/W	0h	Enables frame clock output on DCLKZ pin. Must be enabled in Serial CMOS mode. 0b = Frame clock output on DCLKZ pin disabled 1b = Frame clock output on DCLKZ pin enabled
6	CNL_PDN	R/W	0h	Powers down internal non-linearity correction. Useful for input frequencies above 100 MHz and reduces current by 0.5 mA. 0b = Non-linearity correction enabled 1b = Non-linearity correction powered down
5	BUF_CHB	R/W	0h	Reduces current to ADC channel B input buffer which reduces buffer bandwidth. Recommended for input signals below 25 MHz and reduces current consumption by 2 mA. 0b = Input buffer full power mode 1b = Input buffer low power mode
4	BUF_CHA	R/W	0h	Reduces current to ADC channel A input buffer which reduces buffer bandwidth. Recommended for input signals below 25 MHz. Reduces current consumption by 2 mA. 0b = Input buffer full power mode 1b = Input buffer low power mode
3:0	RESERVED	R	0h

6.6.1.8 DEV_CFG_2 Register (Address = 89h) [Reset = 00h]

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Table 6-14 DEV_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DCLK_FL_DLY__0	R/W	0h	Adjust the delay on the falling edge of DCLK where T is the period of DCLK. 0b = No adjustment 1b = T/20 (T/10 with HFSB = 1) 1010b = -T/10 (-T/5 with HFSB = 1) 1011b = -T/20 (-T/10 with HFSB = 1)
6	DIG_DCLK	R/W	0h	By default CLK is DCLK for digital blocks. Enable when CLK and DCLK are different and DCLKIN is used. 0b = CLK used as DCLK for digital blocks 1b = DCLKIN used as DCLK for digital blocks
5	DIG_DATA	R/W	0h	Data from digital block used as output data. 0b = Digital data to output data disabled 1b = Digital data to output data enabled
4:0	RESERVED	R	0h

6.6.1.9 CLK_CFG_1 Register (Address = 8Ah) [Reset = 00h]

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Table 6-15 CLK_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
5	DIG_CLK_SEL	R/W	0h	By default CLK is DCLK for digital blocks. Enable when CLK and DCLK are different and DCLKIN is used. 0b = CLK used as CLK for digital blocks 1b = Relatched CLK using DCLKIN used as CLK for digital blocks
4	RESERVED	R	0h
3	CHB_CLK	R/W	0h	Enable when only ADC channel A is disabled, ADC channel B is enabled and HDDR interface mode is used.
2:1	DCLK_RISE_DLY	R/W	0h	Adjust the delay on the rising edge of DCLK where T is the period of DCLK. 00b = No adjustment 01b = T/20 (T/10 with HFSB = 1) 10b = -T/10 (-T/5 with HFSB = 1) 11b = -T/20 (-T/10 with HFSB = 1)
0	DCLK_FL_DLY__1	R/W	0h	Adjust the delay on the falling edge of DCLK where T is the period of DCLK. 0b = No adjustment 1b = T/20 (T/10 with HFSB = 1) 10b = -T/10 (-T/5 with HFSB = 1) 11b = -T/20 (-T/10 with HFSB = 1)

6.6.1.10 CLK_CFG_2 Register (Address = 8Bh) [Reset = 00h]

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Table 6-16 CLK_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
5:4	DCLKZ_RISE_DLY	R/W	0h	Adjust the delay on the rising edge of DCLKZ where T is the period of DCLK. 00b = No adjustment 01b = T/20 (T/10 with HFSB = 1) 10b = -T/10 (-T/5 with HFSB = 1) 11b = -T/20 (-T/10 with HFSB = 1)
3	RESERVED	R	0h
2:1	DCLKZ_FALL_DLY	R/W	0h	Adjust the delay on the falling edge of DCLKZ where T is the period of DCLK. 00b = No adjustment 01b = T/20 (T/10 with HFSB = 1) 10b = -T/10 (-T/5 with HFSB = 1) 11b = -T/20 (-T/10 with HFSB = 1)
0	RESERVED	R	0h

6.6.1.11 PDN_CFG Register (Address = 8Ch) [Reset = 00h]

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Table 6-17 PDN_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CHA_PDN	R/W	0h	Powers down ADC channel A. Reduces current by 12 mA. 0b = ADC channel A enabled 1b = ADC channel A powered down
6	CHB_PDN	R/W	0h	Powers down ADC channel B. Reduces current by 12 mA. 0b = ADC channel B enabled 1b = ADC channel B powered down
5	MASK_REF	R/W	0h	Fast power down mask control for reference amplifier. 0b = Reference amplifier powered down when fast power down is exercised. 1b = Reference amplifier NOT powered down when fast power down is exercised.
4	MASK_VCM	R/W	0h	Fast power down mask control for VCM buffer. 0b = VCM buffer powered down when fast power down is exercised. 1b = Reference amplifier NOT powered down when fast power down is exercised.
3	MASK_DLL	R/W	0h	Fast power down mask control for CLK DLL and DCLK DLL. 0b = DLLs powered down when fast power down is exercised. 1b = DLLs NOT powered down when fast power down is exercised.
2	SDR_CHB_SEL	R/W	0h	Selects the channel data to be sent out in SDR interface mode. Enable SDR with Channel B output when asserted. 0b = Channel A data 1b = Channel B data
1:0	RESERVED	R	0h

6.6.1.12 DEV_CFG_3 Register (Address = 8Dh) [Reset = 00h]

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Table 6-18 DEV_CFG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
6	FORMAT	R/W	0h	Output Data Format when digital features are bypassed. 0b = Two's Complement 1b = Offset binary
5:4	RESERVED	R	0h
3	DCLKZ_DLL	R/W	0h	Swap DCLKZ_OUT to DCLK output of DLL 0b = DCLKZ_OUT to DCLKZ output of DLL 1b = DCLKZ_OUT to DCLK output of DLL
2	DCLK_DLL	R/W	0h	Swap DCLK_OUT to DCLKZ output of DLL 0b = DCLK_OUT to DCLK output of DLL 1b = DCLK_OUT to DCLKZ output of DLL
1	ALERT_POL	R/W	0h	ALERT pin polarity 0b = ALERT pin active high 1b = ALERT pin active low
0	RESERVED	R	0h

6.6.1.13 CLK_CFG_3 Register (Address = 8Eh) [Reset = 00h]

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Table 6-19 CLK_CFG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	DCLK_SYNC	R/W	0h	Used for DDR and SDR interface modes 00b = DDR Clocking mode (DCLKZ is inversion of DCLK) 01b = DDR Clocking 1010b = SDR Clocking (DCLKZ is same as DCLK) 1011b = DCLK/DCLKZ off
5:2	RESERVED	R	0h
1	ADLL_BYP	R/W	0h	Bypass analog DLL. Enable this setting when ADC clock frequency below 25MHz. Reduces current by 1mA. 0b = Normal operation 1b = Analog DLL bypassed
0	RESERVED	R	0h

6.6.1.14 CLK_CFG_4 Register (Address = 8Fh) [Reset = 00h]

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Table 6-20 CLK_CFG_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	DCLK_DLL	R/W	0h	Enable when digital features are used
3:0	RESERVED	R	0h

6.6.1.15 PIN_CFG_1 Register (Address = 90h) [Reset = 00h]

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Table 6-21 PIN_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ALERT_OD	R/W	0h	Alert output pin mode 0b = Push-pull 1b = Open-drain
6:4	RESERVED	R	0h
3:1	CLK_PIN_STRENGTH	R/W	0h	DCLK and DCLKZ output pin strength 000b = 15/15 (default) 001b = 13/15 010b = 11/15 011b = 9/15 100b = 7/15 101b = 5/15 110b = 3/15 111b = 1/15
0	RESERVED	R	0h

6.6.1.16 TEST_PAT_CFG Register (Address = 91h) [Reset = 0h]

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Table 6-22 TEST_PAT_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	DATA_PIN_STRENGTH	R/W	0h	D11 to D0 output pin strength 0000b = 15/15 (default) 0001b = 14/15 0010b = 13/15 0011b = 12/15 0100b = 11/15 0101b = 10/15 0110b = 9/15 0111b = 8/15 1000b = 7/15 1001b = 6/15 1010b = 5/15 1011b = 4/15 1100b = 3/15 1101b = 2/15 1110b = 1/15 1111b = 0/15 (Tri-state)

6.6.1.17 TEST_PATTERN_CFG Register (Address = 91h) [Reset = 00h]

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Table 6-23 TEST_PATTERN_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
6	TOGGLE_PAT	R/W	0h	Toggle mode for test pattern. Enable to toggle all lanes in SDR mode, disable in DDR mode. 0b = Disable test pattern toggle 1b = Enable test pattern toggle
5	TEST_PAT_B	R/W	0h	Enables the test pattern in register 0x0092 0b = Channel B test pattern disabled 1b = Channel B test pattern enabled
4	TEST_PAT_A	R/W	0h	Enables the test pattern in register 0x0094 0b = Channel A test pattern disabled 1b = Channel A test pattern enabled
3:0	RESERVED	R	0h

6.6.1.18 TEST_PATTERN_CHB_7:0 Register (Address = 92h) [Reset = 00h]

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Table 6-24 TEST_PATTERN_CHB_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TEST_PATTERN_CHB__7:0	R/W	0h

6.6.1.19 TEST_PATTERN_CHB_13:8 Register (Address = 93h) [Reset = 00h]

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Table 6-25 TEST_PATTERN_CHB_13:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
5:0	TEST_PATTERN_CHB__13:8	R/W	0h

6.6.1.20 TEST_PATTERN_CHA_7:0 Register (Address = 94h) [Reset = 00h]

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Table 6-26 TEST_PATTERN_CHA_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	TEST_PATTERN_CHA__7:0	R/W	0h

6.6.1.21 TEST_PATTERN_CHA_13:8 Register (Address = 95h) [Reset = 00h]

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Table 6-27 TEST_PATTERN_CHA_13:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
5:0	TEST_PATTERN_CHA__13:8	R/W	0h

6.6.1.22 GLOBAL_PDN Register (Address = 97h) [Reset = 00h]

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Table 6-28 GLOBAL_PDN Register Field Descriptions

Bit	Field	Type	Reset	Description
5	PDN	R/W	0h	Global power down via SPI. 0b = Global power down disabled 1b = Global power down enabled.
4:0	RESERVED	R	0h

6.6.1.23 INTERFACE_CFG_1 Register (Address = 98h) [Reset = 00h]

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Table 6-29 INTERFACE_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OENZ_PDN	R/W	0h	Overwrites OENZ control pin as either global or fast power down 0b = OENZ control pin functions as output enable 1b = OENZ control pin functions as power down. Power down options in register 0x009C determine the power down mode.
6	RESERVED	R	0h
5	HDDR_EN	R/W	0h	Enable HDDR interface mode 0b = HDDR interface mode disabled 1b = HDDR interface mode enabled
4	SDR_EN	R/W	0h	Enable SDR interface mode 0b = SDR interface mode disabled 1b = SDR interface mode enabled
3:0	ALERT_PIN_STRENGTH	R/W	0h	ALERT output pin strength 0000b = 15/15 (default) 0001b = 14/15 0010b = 13/15 0011b = 12/15 0100b = 11/15 0101b = 10/15 0110b = 9/15 0111b = 8/15 1000b = 7/15 1001b = 6/15 1010b = 5/15 1011b = 4/15 1100b = 3/15 1101b = 2/15 1110b = 1/15 1111b = 0/15 (Tri-state)

6.6.1.24 INTERFACE_CFG_2 Register (Address = 9Ch) [Reset = 00h]

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Table 6-30 INTERFACE_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
6	OENZ_GPDN	R/W	0h	Overwrites OENZ control pin as global power down. Global power down superseeds fast power down. 0b = OENZ control pin functions as output enable 1b = OENZ control pin functions as global power down
5	OENZ_FPDN	R/W	0h	Overwrites OENZ control pin as fast power down. Global power down superseeds fast power down. 0b = OENZ control pin functions as output enable 1b = OENZ control pin functions as fast power down
4:2	RESERVED	R	0h
1:0	ALERT_PIN_SEL	R/W	0h	Alert output pin function. By default the ALERT output pin monitors overranging at the ADC core. 00b = Channel A overrange (OVR CHA) \|\| Channel B overrange (OVR CHB) 01b = Channel A overrange (OVR CHA) 10b = Channel B overrange (OVR CHB) 11b = Digital Alerts

6.6.1.25 HFSB_FPDN_CFG Register (Address = 9Eh) [Reset = 00h]

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Table 6-31 HFSB_FPDN_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
6:5	HFSB_CONFIG	R/W	0h	DCLK generation block control. Used when global HFSB is 0 (CLK is greater than 65 MSPS) and DCLK is less than 65 MSPS, e.g. decimation. Forces half speed mode on DCLK generation block. 00b = Half speed mode for DCLK disabled 11b = Half speed mode for DCLK enabled
4	PDN_FAST	R/W	0h	Fast power down via SPI. 0b = Fast power down disabled 1b = Fast power down enabled. Power down mask (register 0x008C) determines which internal blocks are powered down.
3:0	RESERVED	R	0h

6.6.1.26 INTERFACE_CFG_3 Register (Address = A0h) [Reset = 00h]

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Table 6-32 INTERFACE_CFG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
5	CHB_SWAP	R/W	0h	Selects the channel data to send on Channel B output. Applicable in DDR interface mode and only available when digital enabled. 0b = Channel B data on channel B output 1b = Channel A data on channel B output
4	CHA_SWAP	R/W	0h	Selects the channel data to send on Channel A output. Applicable in DDR interface mode and only available when digital enabled. 0b = Channel A data on channel A output 1b = Channel B data on channel A output
3	OENZ_PIN_VAL	R/W	0h	Value to be overwritten on OENZ pin. Must enable OENZ overwrite in register 0x00A0, bit 2.
2	OENZ_PIN_OW	R/W	0h	OENZ pin overwrite 0b = Use value on OENZ pin 1b = Use value from OENZ_PIN_ VAL. Ignore value on OENZ pin.
1:0	RESERVED	R	0h

6.6.1.27 DIG_PATTERN_EN Register (Address = A1h) [Reset = 00h]

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Table 6-33 DIG_PATTERN_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
5:3	DIG_PATTERN_MODE_CHB	R/W	0h	Enables test pattern output mode for channel B. 001b = Ramp pattern with step size of 1 010b = Ramp pattern with step size set in DIG PAT CHA 100b = Constant pattern using DIG PAT CHA 101b = Toggle pattern between DIG PAT CHA and bitwise inverted DIG PAT CHA 110b = Toggle pattern between DIG PAT CHA and 0
2:0	DIG_PATTERN_MODE_CHA	R/W	0h	Enables test pattern output mode for channel A. 001b = Ramp pattern with step size of 1 010b = Ramp pattern with step size set in DIG PAT CHA 100b = Constant pattern using DIG PAT CHA 101b = Toggle pattern between DIG PAT CHA and bitwise inverted DIG PAT CHA 110b = Toggle pattern between DIG PAT CHA and 0

6.6.1.28 DIG_PATTERN_CHA_7:0 Register (Address = A2h) [Reset = 00h]

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Table 6-34 DIG_PATTERN_CHA_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DIG_PATTERN_CHA__7:0	R/W	0h	Used with DIG PAT MODE CHA to set constant custom pattern starting from MSB or sets ramp pattern increment step size.

6.6.1.29 DIG_PATTERN_CHA_15:8 Register (Address = A3h) [Reset = 00h]

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Table 6-35 DIG_PATTERN_CHA_15:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DIG_PATTERN_CHA__15:8	R/W	0h	Used with DIG PAT MODE CHA to set constant custom pattern starting from MSB or sets ramp pattern increment step size.

6.6.1.30 DIG_PATTERN_CHB_7:0 Register (Address = A4h) [Reset = 00h]

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Table 6-36 DIG_PATTERN_CHB_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DIG_PATTERN_CHB__7:0	R/W	0h	Used with DIG PAT MODE CHB to set constant custom pattern starting from MSB or sets ramp pattern increment step size.

6.6.1.31 DIG_PATTERN_CHB_15:8 Register (Address = A5h) [Reset = 00h]

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Table 6-37 DIG_PATTERN_CHB_15:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DIG_PATTERN_CHB__15:8	R/W	0h	Used with DIG PAT MODE CHB to set constant custom pattern starting from MSB or sets ramp pattern increment step size.

6.6.1.32 INTERFACE_CFG_4 Register (Address = A6h) [Reset = 00h]

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Table 6-38 INTERFACE_CFG_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
5	DDR_MODE	R/W	0h	Channel data output order. Applicable in DDR interface mode. 0b = Channel A data on rising edge and channel B on falling edge of DCLK 1b = Channel A data outputed first then channel B data
4:1	SERIALIZATION	R/W	0h	Serialization Factor 0000b = Parellel output 0001b = 2x serialization 0010b = 4x serialization 0011b = 8x serialization 0100b = 16x serialization
0	DIG_PAT_EN	R/W	0h	Enables the test patterns set in DIG PAT MODE CHA and DIG PAT MODE CHB. 0b = Normal output mode (test pattern disabled) 1b = Test pattern enabled

6.6.1.33 OUTPUT_DATA_WIDTH Register (Address = A7h) [Reset = 50h]

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Table 6-39 OUTPUT_DATA_WIDTH Register Field Descriptions

Bit	Field	Type	Reset	Description
4:0	OUTPUT_DATA_WIDTH	R/W	Ah	Output resolution for lane optimization in serialization modes. 01000b = 8-bit 01010b = 10-bit 01100b = 12-bit 10000b = 16-bit

6.6.1.34 DCLK_DIVIDER Register (Address = A8h) [Reset = 0h]

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Table 6-40 DCLK_DIVIDER Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	DCLK_DIVIDER	R/W	0h	Division of CLK to DCLK to match serialization and decimation data rates. Decimation and serialization factor (SERIALIZATION) must match. 0000b = Divide-by-1 0001b = Divide-by-2 0011b = Divide-by-4 0111b = Divide-by-8 1111b = Divide-by-16

6.6.1.35 OUTPUT_BIT_MAPPER_D0_D1 Register (Address = AEh) [Reset = D6h]

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Table 6-41 OUTPUT_BIT_MAPPER_D0_D1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	OUTPUT_BIT_MAPPER_D1	R/W	Dh	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)
3:0	OUTPUT_BIT_MAPPER_D0	R/W	6h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)

6.6.1.36 OUTPUT_BIT_MAPPER_D2_D3 Register (Address = AFh) [Reset = EBh]

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Table 6-42 OUTPUT_BIT_MAPPER_D2_D3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	OUTPUT_BIT_MAPPER_D3	R/W	Eh	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)
3:0	OUTPUT_BIT_MAPPER_D2	R/W	Bh	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)

6.6.1.37 OUTPUT_BIT_MAPPER_D4_D5 Register (Address = B0h) [Reset = 84h]

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Table 6-43 OUTPUT_BIT_MAPPER_D4_D5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	OUTPUT_BIT_MAPPER_D5	R/W	8h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)
3:0	OUTPUT_BIT_MAPPER_D4	R/W	4h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)

6.6.1.38 OUTPUT_BIT_MAPPER_D6_D7 Register (Address = B1h) [Reset = 86h]

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Table 6-44 OUTPUT_BIT_MAPPER_D6_D7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	OUTPUT_BIT_MAPPER_D7	R/W	8h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)
3:0	OUTPUT_BIT_MAPPER_D6	R/W	6h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)

6.6.1.39 OUTPUT_BIT_MAPPER_D8_D9 Register (Address = B2h) [Reset = 92h]

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Table 6-45 OUTPUT_BIT_MAPPER_D8_D9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	OUTPUT_BIT_MAPPER_D9	R/W	9h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)
3:0	OUTPUT_BIT_MAPPER_D8	R/W	2h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)

6.6.1.40 OUTPUT_BIT_MAPPER_D10_D11 Register (Address = B3h) [Reset = 93h]

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Table 6-46 OUTPUT_BIT_MAPPER_D10_D11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	OUTPUT_BIT_MAPPER_D11	R/W	9h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)
3:0	OUTPUT_BIT_MAPPER_D10	R/W	3h	These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB)

6.6.1.41 ROUND Register (Address = B6h) [Reset = 00h]

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Table 6-47 ROUND Register Field Descriptions

Bit	Field	Type	Reset	Description
4	ROUND	R/W	0h	The device uses a 16-bit resolution internally which can be useful for high decimation settings so that the quantization noise doesn't impact the ADC performance. 0b = Truncate 4 LSBs to reduce resolution from 16 bits to resolution specified in OUTPUT DATA WIDTH 1b = Round to reduce resolution from 16 bits to resolution specified in OUTPUT DATA WIDTH
3:0	RESERVED	R	0h

6.6.1.42 COMP_THRESHOLD_HI_CHA_7:0 Register (Address = C8h) [Reset = 00h]

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Table 6-48 COMP_THRESHOLD_HI_CHA_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	COMP_THRESHOLD_HI_CHA__7:0	R/W	0h	Comparator high threshold for channel A

6.6.1.43 COMP_THRESHOLD_HI_CHA_11:8 Register (Address = C9h) [Reset = 0h]

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Table 6-49 COMP_THRESHOLD_HI_CHA_11:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	COMP_THRESHOLD_HI_CHA__11:8	R/W	0h	Comparator high threshold for channel A

6.6.1.44 COMP_THRESHOLD_HI_CHB_7:0 Register (Address = CAh) [Reset = 00h]

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Table 6-50 COMP_THRESHOLD_HI_CHB_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	COMP_THRESHOLD_HI_CHB__7:0	R/W	0h	Comparator high threshold for channel B

6.6.1.45 COMP_THRESHOLD_HI_CHB_11:8 Register (Address = CBh) [Reset = 0h]

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Table 6-51 COMP_THRESHOLD_HI_CHB_11:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	COMP_THRESHOLD_HI_CHB__11:8	R/W	0h	Comparator high threshold for channel B

6.6.1.46 COMP_THRESHOLD_LO_CHA_7:0 Register (Address = CCh) [Reset = 00h]

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Table 6-52 COMP_THRESHOLD_LO_CHA_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	COMP_THRESHOLD_LO_CHA__7:0	R/W	0h	Comparator low threshold for channel A

6.6.1.47 COMP_THRESHOLD_LO_CHA_11:8 Register (Address = CDh) [Reset = 0h]

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Table 6-53 COMP_THRESHOLD_LO_CHA_11:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	COMP_THRESHOLD_LO_CHA__11:8	R/W	0h	Comparator low threshold for channel A

6.6.1.48 COMP_THRESHOLD_LO_CHB_7:0 Register (Address = CEh) [Reset = 00h]

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Table 6-54 COMP_THRESHOLD_LO_CHB_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	COMP_THRESHOLD_LO_CHB__7:0	R/W	0h	Comparator low threshold for channel B

6.6.1.49 COMP_THRESHOLD_LO_CHB_11:8 Register (Address = CFh) [Reset = 0h]

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Table 6-55 COMP_THRESHOLD_LO_CHB_11:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	COMP_THRESHOLD_LO_CHB__11:8	R/W	0h	Comparator low threshold for channel B

6.6.1.50 COMP_HYSTERESIS_CHA_7:0 Register (Address = D0h) [Reset = 00h]

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Table 6-56 COMP_HYSTERESIS_CHA_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	COMP_HYSTERESIS_CHA__7:0	R/W	0h	Comparator hysteresis for channel A

6.6.1.51 COMP_HYSTERESIS_CHA_11:8 Register (Address = D1h) [Reset = 0h]

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Table 6-57 COMP_HYSTERESIS_CHA_11:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	COMP_HYSTERESIS_CHA__11:8	R/W	0h	Comparator hysteresis for channel A

6.6.1.52 COMP_HYSTERISIS_CHB_7:0 Register (Address = D2h) [Reset = 00h]

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Table 6-58 COMP_HYSTERISIS_CHB_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	COMP_HYSTERISIS_CHB__7:0	R/W	0h	Comparator hysteresis for channel A

6.6.1.53 COMP_HYSTERISIS_CHB_11:8 Register (Address = D3h) [Reset = 0h]

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Table 6-59 COMP_HYSTERISIS_CHB_11:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	COMP_HYSTERISIS_CHB__11:8	R/W	0h	Comparator hysteresis for channel A

6.6.1.54 COMP_SLEW Register (Address = D3h) [Reset = 00h]

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Table 6-60 COMP_SLEW Register Field Descriptions

Bit	Field	Type	Reset	Description
5	SLEW_CHB	R/W	0h	Comparison method for channel B 0b = Standard compare (THRESHOLD HI CHB - HYSTERESIS CHB, THRESHOLD LO CHB + HYSTERESIS CHB) 1b = Slew compare (current sample - previous sample > THRESHOLD HI CHB, current sample - previous sample < THRESHOLD LO CHB) HYSTERESIS CHB must be set to 0.
4	SLEW_CHA	R/W	0h	Comparison method for channel A 0b = Standard compare (THRESHOLD HI CHA - HYSTERESIS CHA, THRESHOLD LO CHA + HYSTERESIS CHA) 1b = Slew compare (current sample - previous sample > THRESHOLD HI CHA, current sample - previous sample < THRESHOLD LO CHA) HYSTERESIS CHA must be set to 0.
3:0	RESERVED	R	0h

6.6.1.55 DECIMATION Register (Address = D4h) [Reset = 0h]

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Table 6-61 DECIMATION Register Field Descriptions

Bit	Field	Type	Reset	Description
3	DDC_CHB	R/W	0h	Channel B decimation 0b = Decimation disabled 1b = Decimation enabled
2	DDC_CHA	R/W	0h	Channel A decimation 0b = Decimation disabled 1b = Decimation enabled
1:0	RESERVED	R	0h

6.6.1.56 PROG_GAIN_CHA Register (Address = D5h) [Reset = 00h]

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Table 6-62 PROG_GAIN_CHA Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PROG_GAIN_CHA	R/W	0h	Programmable gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15.

6.6.1.57 PROG_GAIN_CHB Register (Address = D6h) [Reset = 00h]

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Table 6-63 PROG_GAIN_CHB Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PROG_GAIN_CHB	R/W	0h	Programmable gain for channel B. Effective gain = (PROG GAIN CHB * 256 + IL GAIN CHB)/2**15

6.6.1.58 IL_GAIN_CHA_7:0 Register (Address = D8h) [Reset = 00h]

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Table 6-64 IL_GAIN_CHA_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	IL_GAIN_CHA__7:0	R/W	0h	Interleaving gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15

6.6.1.59 IL_GAIN_CHA_15:8 Register (Address = D9h) [Reset = 00h]

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Table 6-65 IL_GAIN_CHA_15:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	IL_GAIN_CHA__15:8	R/W	0h	Interleaving gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15

6.6.1.60 IL_GAIN_CHB_7:0 Register (Address = DAh) [Reset = 00h]

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Table 6-66 IL_GAIN_CHB_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	IL_GAIN_CHB__7:0	R/W	0h	Interleaving gain for channel B. Effective gain = (PROG GAIN CHB * 256 + IL GAIN CHB)/2**15

6.6.1.61 IL_GAIN_CHB_15:8 Register (Address = DBh) [Reset = 00h]

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Table 6-67 IL_GAIN_CHB_15:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	IL_GAIN_CHB__15:8	R/W	0h	Interleaving gain for channel B. Effective gain = (PROG GAIN CHB * 256 + IL GAIN CHB)/2**15

6.6.1.62 OFFSET_CHA_7:0 Register (Address = DCh) [Reset = 00h]

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Table 6-68 OFFSET_CHA_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	OFFSET_CHA__7:0	R/W	0h	Channel A offset. Effective offset = OFFSET CHA/2**15

6.6.1.63 OFFSET_CHA_15:8 Register (Address = DDh) [Reset = 00h]

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Table 6-69 OFFSET_CHA_15:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	OFFSET_CHA__15:8	R/W	0h	Channel A offset. Effective offset = OFFSET CHA/2**15

6.6.1.64 OFFSET_CHB_7:0 Register (Address = DEh) [Reset = 00h]

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Table 6-70 OFFSET_CHB_7:0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	OFFSET_CHB__7:0	R/W	0h	Channel B offset. Effective offset = OFFSET CHB/2**15

6.6.1.65 OFFSET_CHB_15:8 Register (Address = DFh) [Reset = 00h]

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Table 6-71 OFFSET_CHB_15:8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	OFFSET_CHB__15:8	R/W	0h	Channel B offset. Effective offset = OFFSET CHB/2**15

6.6.1.66 CH_CORR_EN Register (Address = E0h) [Reset = 3h]

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Table 6-72 CH_CORR_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
1	CORR_CHB__15:8	R/W	1h	Channel corrections for channel B (PROG GAIN CHB, IL GAIN CHB, OFFSET CHB) 0b = Channel corrections enabled 1b = Channel corrections disabled
0	CORR_CHA__7:0	R/W	1h	Channel corrections for channel A (PROG GAIN CHA, IL GAIN CHA, OFFSET CHA) 0b = Channel corrections enabled 1b = Channel corrections disabled

6.6.1.67 DDC_CFG_1 Register (Address = 200h) [Reset = 00h]

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Table 6-73 DDC_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
5:3	DDC_DATA_SEL_CHA	R/W	0h	Data select for channel A decimation 000b = ADC channel A (default) 001b = ADC channel B
2:0	DECIMATION	R/W	0h	Real decimation setting. This applies to both channels. 000b = Bypass mode (no decimation) 001b = Decimation by 2 010b = Decimation by 4 011b = Decimation by 8 100b = Decimation by 16

6.6.1.68 STATS_COMP_DATA_SEL Register (Address = 201h) [Reset = 00h]

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Table 6-74 STATS_COMP_DATA_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
5:3	STATS_DATA_SEL_CHA	R/W	0h	Data select for channel A statistics engine 000b = Channel A digital downconverter 001b = ADC channel B 100b = Average of channel A and channel B data 101b = Channel A correction block 110b = Channel B correction block
2:0	COMP_DATA_SEL_CHA	R/W	0h	Data select for channel A comparator 000b = Channel A digital downconverter 001b = ADC channel B 100b = Average of channel A and channel B data 101b = Channel A correction block 110b = Channel B correction block

6.6.1.69 OUTPUT_DATA_SEL Register (Address = 202h) [Reset = 0h]

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Table 6-75 OUTPUT_DATA_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
2:0	OUTPUT_DATA_SEL_CHA	R/W	0h	Data select for channel A output 000b = Channel A digital downconverter 001b = ADC channel B 100b = Average of channel A and channel B data 101b = Channel A correction block 110b = Channel B correction block

6.6.1.70 COMP_DDC_DATA_SEL Register (Address = 203h) [Reset = 21h]

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Table 6-76 COMP_DDC_DATA_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
5:3	COMP_DATA_SEL_CHB	R/W	1h	Data select for channel B comparator 000b = Channel A digital downconverter 001b = ADC channel B (default) 100b = Average of channel A and channel B data 101b = Channel A correction block 110b = Channel B correction block
2:0	DDC_DATA_SEL_CHB	R/W	1h	Data select for channel B decimation 000b = ADC channel A 001b = ADC channel B (default)

6.6.1.71 OUTPUT_STATS_DATA_SEL Register (Address = 204h) [Reset = 21h]

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Table 6-77 OUTPUT_STATS_DATA_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
5:3	OUTPUT_DATA_SEL_CHB	R/W	1h	Data select for channel B output 000b = Channel A digital downconverter 001b = ADC channel B (default) 100b = Average of channel A and channel B data 101b = Channel A correction block 110b = Channel B correction block
2:0	STATS_DATA_SEL_CHB	R/W	1h	Data select for channel B statistics engine 000b = Channel A digital downconverter 001b = ADC channel B (default) 100b = Average of channel A and channel B data 101b = Channel A correction block 110b = Channel B correction block

6.6.1.72 OVR_CHB Register (Address = 205h) [Reset = F0h]

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Table 6-78 OVR_CHB Register Field Descriptions

Bit	Field	Type	Reset	Description
6:3	OVR_CHB	R/W	Fh	Channel B overrange control. This register is a mask with all sources enabled by default. Bit 0: Truncation overrange Bit 1: Channel Correction overrange Bit 2: Decimation overrange Bit 3: ADC overrange
2:0	RESERVED	R	0h

6.6.1.73 OVR_CHA Register (Address = 206h) [Reset = Fh]

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Table 6-79 OVR_CHA Register Field Descriptions

Bit	Field	Type	Reset	Description
3:0	OVR_CHA	R	Fh	Channel A overrange control. This register is a mask with all sources enabled by default. Bit 0: Truncation overrange Bit 1: Channel Correction overrange Bit 2: Decimation overrange Bit 3: ADC overrange

6.6.1.74 CLK_TIM_ADJ_CHA Register (Address = 304h) [Reset = 00h]

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Table 6-80 CLK_TIM_ADJ_CHA Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	CLK_TIM_ADJ_CHA	R/W	0h	ADC channel A sampling edge adjustment. Used in interleaved mode to reduce interleaving spur. Min. step size is 1 ps and adjustment range is 15 ps.
0	RESERVED	R	0h

6.6.1.75 CLK_TIM_ADJ_CHB Register (Address = 305h) [Reset = 00h]

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Table 6-81 CLK_TIM_ADJ_CHB Register Field Descriptions

Bit	Field	Type	Reset	Description
7	DCLK_OUT	R/W	0h	DCLK output disable 0b = DCLK output enabled 1b = DCLK output disabled
6:0	CLK_TIM_ADJ_CHB	R/W	0h	ADC channel B sampling edge adjustment. Used in interleaved mode to reduce interleaving spur. Min. step size is 1 ps and adjustment range is 15 ps.

6.6.1.76 DCLK_DLL_PD Register (Address = 306h) [Reset = 0h]

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Table 6-82 DCLK_DLL_PD Register Field Descriptions

Bit	Field	Type	Reset	Description
0	DCLKDLL_PD	R/W	0h	DCLK DLL power down and bypass. Useful in SDR interface mode and reduces current by 1 mA. 0b = DCLK DLL enabled 1b = DCLK DLL power down and bypassed

6.6.1.77 DIG_INPUT_CFG Register (Address = 307h) [Reset = 00h]

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Table 6-83 DIG_INPUT_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
4	DCLKZ_OUT	R/W	0h	DCLKZ output disable 0b = DCLKZ output enabled 1b = DCLKZ output disabled
3	DIG_INPUT	R/W	0h	Disables data inputs to digital block. 0b = Data inputs enabled to digital blocks 1b = Data input disabled to digital blocks
2:0	RESERVED	R	0h

6.6.1.78 BUF_VCM_CURR Register (Address = 309h) [Reset = 00h]

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Table 6-84 BUF_VCM_CURR Register Field Descriptions

Bit	Field	Type	Reset	Description
5:4	BUF_CURR_CHB__1:0	R/W	0h	ADC channel B input buffer PTAT current source mask LSB's used for gain tracking across temperature for stability. 00b = 19.9uA (default) 01b = 26.5uA 10b = 13.3uA 11b = 19.9uA 100b = 29.9uA 101b = 36.5uA 110b = 23.3uA 111b = 29.9uA 1000b = 6.6uA 1001b = 13.2uA 1010b = 0uA 1011b = 6.6uA 1100b = 16.6uA 1101b = 23.2uA 1110b = 10uA 1111b = 16.6uA
3:0	VCM_CURR	R/W	0h	VCM buffer PTAT current source mask used for gain tracking across temperature for stability. 0000b = 19.9uA (default) 0001b = 26.5uA 0010b = 13.3uA 0011b = 19.9uA 0100b = 29.9uA 0101b = 36.5uA 0110b = 23.3uA 0111b = 29.9uA 1000b = 6.6uA 1001b = 13.2uA 1010b = 0uA 1011b = 6.6uA 1100b = 16.6uA 1101b = 23.2uA 1110b = 10uA 1111b = 16.6uA

6.6.1.79 BUF_CURR Register (Address = 30Ah) [Reset = 00h]

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Table 6-85 BUF_CURR Register Field Descriptions

Bit	Field	Type	Reset	Description
6	FORMAT_DIG	R/W	0h	Output Data Format when digital features are used. 0b = Two's Complement 1b = Offset binary
5:2	BUF_CURR_CHA	R/W	0h	ADC channel A input buffer PTAT current source mask used for gain tracking across temperature for stability. 0000b = 19.9uA (default) 0001b = 26.5uA 0010b = 13.3uA 0011b = 19.9uA 0100b = 29.9uA 0101b = 36.5uA 0110b = 23.3uA 0111b = 29.9uA 1000b = 6.6uA 1001b = 13.2uA 1010b = 0uA 1011b = 6.6uA 1100b = 16.6uA 1101b = 23.2uA 1110b = 10uA 1111b = 16.6uA
1:0	BUF_CURR_CHB__3:2	R/W	0h	ADC channel B input buffer PTAT current source mask LSB's used for gain tracking across temperature for stability. 00b = 19.9uA (default) 01b = 26.5uA 10b = 13.3uA 11b = 19.9uA 100b = 29.9uA 101b = 36.5uA 110b = 23.3uA 111b = 29.9uA 1000b = 6.6uA 1001b = 13.2uA 1010b = 0uA 1011b = 6.6uA 1100b = 16.6uA 1101b = 23.2uA 1110b = 10uA 1111b = 16.6uA

6.6.1.80 DEV_CFG_4 Register (Address = 30Bh) [Reset = 00h]

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Table 6-86 DEV_CFG_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
6	EXT_REF	R/W	0h	Selects the voltage reference option 0b = Internal reference 1b = External reference
5	SE_EN	R/W	0h	Single ended analog input for ADC channels A and B. In this mode the SNR reduces by 3-dB. 0b = Differential input 1b = Single ended input
4	SINGLE_CH	R/W	0h	Disables ADC channel B 0b = ADC channel B enabled 1b = ADC channel B disabled (enforced on single channel devices)
3	RESERVED	R	0h
2	HALF_SPEED	R/W	0h	Half speed mode (HFSB). Enable when sample clock is less than 65 MSPS. 0b = Half speed mode disabled 1b = Half speed mode enabled (enforced on 25MSPS and 65MSPS devices)
1	RESERVED	R	0h
0	8BIT_EN	R/W	0h	ADC resolution 0b = 10-bit resolution 1b = 8-bit resolution

6.6.1.81 GBL_CLK_CFG_1 Register (Address = 484h) [Reset = 0h]

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Table 6-87 GBL_CLK_CFG_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
1	CLK_GBL	R/W	0h	Global clock enable. Controls clock for digital block 0b = Gates clock to digital 1b = Ungates clock to digital
0	RESERVED	R	0h

6.6.1.82 GBL_CLK_CFG_2 Register (Address = 4BEh) [Reset = 00h]

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Table 6-88 GBL_CLK_CFG_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	CLK_STATS	R/W	0h	Controls clock to statistics engine 00b = Disables clock to statistics engine 11b = Enables clock to statistics engine
5:4	CLK_COMP	R/W	0h	Controls clock to comparator 00b = Disables clock to comparator 11b = Enables clock to comparator
3:2	CLK_DEC	R/W	0h	Controls clock to decimation 00b = Disables clock to decimation 11b = Enables clock to decimation
1:0	CLK_CC	R/W	0h	Controls clock to channel corrections 00b = Disables clock to channel corrections 11b = Enables clock to channel corrections

6.6.1.83 GBL_CLK_CFG_3 Register (Address = 4BFh) [Reset = 0h]

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Table 6-89 GBL_CLK_CFG_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
1:0	CLK_OUT	R/W	0h	Controls clock to digital output block 00b = Disables clock to digital output 11b = Enables clock to digital output