JAJSP39A May   2022  – December 2022 ADS1285

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V
    7. 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 PGA and Buffer
        1. 8.3.2.1 Programmable Gain Amplifier (PGA)
        2. 8.3.2.2 Buffer Operation (PGA Bypass)
      3. 8.3.3 Voltage Reference Input
      4. 8.3.4 IOVDD Power Supply
      5. 8.3.5 Modulator
        1. 8.3.5.1 Modulator Overdrive
      6. 8.3.6 Digital Filter
        1. 8.3.6.1 Sinc Filter Section
        2. 8.3.6.2 FIR Filter Section
        3. 8.3.6.3 Group Delay and Step Response
          1. 8.3.6.3.1 Linear Phase Response
          2. 8.3.6.3.2 Minimum Phase Response
        4. 8.3.6.4 HPF Stage
      7. 8.3.7 Clock Input
      8. 8.3.8 GPIO
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Reset
      4. 8.4.4 Synchronization
        1. 8.4.4.1 Pulse-Sync Mode
        2. 8.4.4.2 Continuous-Sync Mode
      5. 8.4.5 Sample Rate Converter
      6. 8.4.6 Offset and Gain Calibration
        1. 8.4.6.1 OFFSET Register
        2. 8.4.6.2 GAIN Register
        3. 8.4.6.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Output (DOUT)
        5. 8.5.1.5 Data Ready (DRDY)
      2. 8.5.2 Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1  Single Byte Command
        2. 8.5.3.2  WAKEUP: Wake Command
        3. 8.5.3.3  STANDBY: Software Power-Down Command
        4. 8.5.3.4  SYNC: Synchronize Command
        5. 8.5.3.5  RESET: Reset Command
        6. 8.5.3.6  Read Data Direct
        7. 8.5.3.7  RDATA: Read Conversion Data Command
        8. 8.5.3.8  RREG: Read Register Command
        9. 8.5.3.9  WREG: Write Register Command
        10. 8.5.3.10 OFSCAL: Offset Calibration Command
        11. 8.5.3.11 GANCAL: Gain Calibration Command
    6. 8.6 Register Map
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
        4. 8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
        5. 8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
        6. 8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
        7. 8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
        8. 8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Analog Power Supplies
      2. 9.3.2 Digital Power Supply
      3. 9.3.3 Grounds
      4. 9.3.4 Thermal Pad
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • RHB|32
サーマルパッド・メカニカル・データ
発注情報

7.1 Noise Performance

The ADS1285 is a 32-bit ADC providing three power-resolution modes, allowing optimization of noise performance verses device power consumption. The four determining factors of noise performance are the power mode, output data rate, PGA gain setting, and reference voltage selection. The high-power mode operates the PGA and modulator sampling rate at the highest capacity for best overall noise performance. The mid-power mode scales down the PGA quiescent current to reduce power consumption but results in increased PGA noise. The low-power mode reduces both the modulator sampling rate and PGA quiescent current. The result is the low-power mode has the lowest power consumption but the highest level of overall noise.

For all power modes, decreasing the output data rate reduces signal bandwidth, and therefore decreases total noise. Increasing the PGA gain reduces noise when noise is referred to the input. Dynamic range performance decreases when PGA gain is increased because the ratio of input voltage range to input-referred noise also decreases.

Noise performance also depends on the reference voltage. Operation with VREF = 4.096 V or 5 V provides the best noise performance. Operation with VREF = 2.5 V (required when operating AVDD1 = 3.3 V) reduces noise performance.

Dynamic range and input noise are equivalent parameters that describe the available resolution of the ADC. Equation 1 derives dynamic range from the input-referred noise data:

Equation 1.

where:

  • en = Input-referred voltage noise (RMS)

Figure 7-1 and Figure 7-2 show dynamic range performance at fDATA = 500 SPS for operation with VREF = 4.096 V and VREF = 2.5 V.

fDATA = 500 SPS, VREF = 4.096 V
Figure 7-1 Dynamic Range vs PGA Gain
fDATA = 500 SPS, VREF = 2.5 V
Figure 7-2 Dynamic Range vs PGA Gain

Table 7-1 through Table 7-3 list dynamic range and input-referred noise performance with VREF = 4.096 V and AVDD1 = 5 V, tested with input source resistance (RS) = 0 Ω. Table 7-4 through Table 7-6 list dynamic range and input noise performance with VREF = 2.5 V and AVDD1 = 3.3 V, tested with RS = 0 Ω. Noise data are at TA = 25°C and are representative of typical ADC performance. The data are the standard deviation of 4096 consecutive ADC conversion results with the ADC inputs shorted, measured over the 0.413 × fDATA bandwidth. Because of the statistical nature of noise, repeated measurements can yield varying noise performance results.

Table 7-1 High-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω)
GAIN MODE DYNAMIC RANGE (dB) en, INPUT-REFERRED NOISE (μVRMS)
fDATA fDATA
250 500 1000 2000 4000 250 500 1000 2000 4000
1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25
1 PGA 137 134 131 128 125 0.25 0.35 0.50 0.70 0.99
2 PGA 136 133 130 127 124 0.14 0.20 0.28 0.39 0.56
4 PGA 134 131 128 125 122 0.09 0.12 0.18 0.25 0.35
8 PGA 130 127 124 121 118 0.07 0.10 0.14 0.20 0.28
16 PGA 126 123 120 117 114 0.06 0.08 0.11 0.16 0.22
32 PGA 120 117 114 111 108 0.06 0.08 0.11 0.16 0.22
64 PGA 114 111 108 105 102 0.06 0.08 0.11 0.16 0.22
Table 7-2 Mid-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω)
GAIN MODE DYNAMIC RANGE (dB) en, INPUT-REFERRED NOISE (μVRMS)
fDATA fDATA
250 500 1000 2000 4000 250 500 1000 2000 4000
1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25
1 PGA 137 134 131 128 125 0.25 0.35 0.50 0.70 0.99
2 PGA 135 132 129 126 123 0.16 0.22 0.31 0.44 0.63
4 PGA 133 130 127 124 121 0.10 0.14 0.20 0.28 0.39
8 PGA 128 125 122 119 116 0.09 0.12 0.18 0.25 0.35
16 PGA 123 120 117 114 111 0.08 0.11 0.16 0.22 0.31
32 PGA 117 114 111 108 105 0.08 0.11 0.16 0.22 0.31
64 PGA 111 108 105 102 99 0.08 0.11 0.16 0.22 0.31
Table 7-3 Low-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω)
GAIN MODE DYNAMIC RANGE (dB) en, INPUT-REFERRED NOISE (μVRMS)
fDATA fDATA
125 250 500 1000 2000 125 250 500 1000 2000
1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25
1 PGA 138 135 132 129 126 0.22 0.31 0.44 0.63 0.89
2 PGA 137 134 131 128 125 0.12 0.18 0.25 0.35 0.50
4 PGA 135 132 129 126 123 0.08 0.11 0.16 0.22 0.31
8 PGA 131 128 125 122 119 0.06 0.09 0.12 0.18 0.25
16 PGA 126 123 120 117 114 0.06 0.08 0.11 0.16 0.22
32 PGA 120 117 114 111 108 0.06 0.08 0.11 0.16 0.22
64 PGA 114 111 108 105 102 0.06 0.08 0.11 0.16 0.22
Table 7-4 High-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω)
GAIN MODE DYNAMIC RANGE (dB) en, INPUT-REFERRED NOISE (μVRMS)
fDATA fDATA
250 500 1000 2000 4000 250 500 1000 2000 4000
1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25
1(1) PGA 128 125 122 119 116 0.35 0.50 0.70 0.99 1.40
2 PGA 133 130 127 124 121 0.20 0.28 0.39 0.56 0.79
4 PGA 132 129 126 123 120 0.11 0.16 0.22 0.31 0.44
8 PGA 129 126 123 120 117 0.08 0.11 0.16 0.22 0.31
16 PGA 125 122 119 116 113 0.06 0.09 0.12 0.18 0.25
32 PGA 119 116 113 110 107 0.06 0.09 0.12 0.17 0.25
64 PGA 113 110 107 104 101 0.06 0.09 0.12 0.17 0.25
Table 7-5 Mid-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω)
GAIN MODE DYNAMIC RANGE (dB) en, INPUT-REFERRED NOISE (μVRMS)
fDATA fDATA
250 500 1000 2000 4000 250 500 1000 2000 4000
1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25
1(1) PGA 128 125 122 119 116 0.35 0.50 0.70 0.99 1.40
2 PGA 133 130 127 124 121 0.20 0.28 0.39 0.56 0.79
4 PGA 131 128 125 122 119 0.12 0.18 0.25 0.35 0.50
8 PGA 127 124 121 118 115 0.10 0.14 0.20 0.28 0.39
16 PGA 123 120 117 114 111 0.08 0.11 0.16 0.22 0.31
32 PGA 117 114 111 108 105 0.08 0.11 0.16 0.22 0.31
64 PGA 111 108 105 102 99 0.08 0.11 0.16 0.22 0.31
Table 7-6 Low-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω)
GAIN MODE DYNAMIC RANGE (dB) en, INPUT-REFERRED NOISE (μVRMS)
fDATA fDATA
125 250 500 1000 2000 125 250 500 1000 2000
1 Buffer 135 132 129 126 123 0.31 0.44 0.63 0.89 1.25
1(1) PGA 129 126 123 120 117 0.31 0.44 0.83 0.89 1.25
2 PGA 134 131 128 125 122 0.18 0.25 0.35 0.50 0.70
4 PGA 133 130 127 124 121 0.10 0.14 0.20 0.28 0.39
8 PGA 130 127 124 121 118 0.07 0.10 0.14 0.20 0.28
16 PGA 125 122 119 116 113 0.06 0.09 0.12 0.17 0.25
32 PGA 119 116 113 110 107 0.06 0.09 0.12 0.17 0.25
64 PGA 113 110 107 104 101 0.06 0.09 0.12 0.17 0.25
(1) Because of the limited input headroom with AVDD1 = 3.3 V operation, the available input range with PGA gain operation = 1 is ±1.35 VPP. The dynamic range data for PGA gain = 1 and AVDD1 = 3.3 V reflects the reduced input range.