JAJSH04C May   2013  – March 2019 ADS8866


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      ADC 電源用に別個の LDO が不要
  4. 改訂履歴
  5. 概要(続き)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: 3-Wire Operation
    7. 8.7 Timing Requirements: 4-Wire Operation
    8. 8.8 Timing Requirements: Daisy-Chain
    9. 8.9 Typical Characteristics
  9. Parameter Measurement Information
    1. 9.1 Equivalent Circuits
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Analog Input
      2. 10.3.2 Reference
      3. 10.3.3 Clock
      4. 10.3.4 ADC Transfer Function
    4. 10.4 Device Functional Modes
      1. 10.4.1 CS Mode
        1. 3-Wire CS Mode
        2. 4-Wire CS Mode
      2. 10.4.2 Daisy-Chain Mode
        1. Daisy-Chain Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 ADC Reference Driver
      2. 11.1.2 ADC Input Driver
        1. Input Amplifier Selection
        2. Charge-Kickback Filter
    2. 11.2 Typical Applications
      1. 11.2.1 DAQ Circuit for a 10-µs, Full-Scale Step Response
        1. Design Requirements
        2. Detailed Design Procedure
      2. 11.2.2 DAQ Circuit for Lowest Distortion and Noise Performance at 100 kSPS
        1. Design Requirements
        2. Detailed Design Procedure
      3. 11.2.3 Ultralow-Power DAQ Circuit at 10 kSPS
        1. Design Requirements
        2. Detailed Design Procedure
  12. 12Power Supply Recommendations
    1. 12.1 Power-Supply Decoupling
    2. 12.2 Power Saving
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 ドキュメントのサポート
      1. 14.1.1 関連資料
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報



Daisy-Chain Mode

This interface option is most useful in applications where multiple ADC devices are used but the digital host has limited interfacing capability. Figure 49 shows a connection diagram with N ADCs connected in the daisy-chain. The CONVST pins of all ADCs in the chain are connected together and are controlled by a single pin of the digital host. Similarly, the SCLK pins of all ADCs in the chain are connected together and are controlled by a single pin of the digital host. The DIN pin for ADC 1 (DIN-1) is connected to GND. The DOUT pin of ADC 1 (DOUT-1) is connected to the DIN pin of ADC 2 (DIN-2), and so on. The DOUT pin of the last ADC in the chain (DOUT-N) is connected to the SDI pin of the digital host.

ADS8866 ai_daisy_conex_v1_bas557.gifFigure 49. Connection Diagram: Daisy-Chain Mode (DIN = 0)

As shown in Figure 50, the device DOUT pin is driven low when DIN and CONVST are low together. With DIN low, a CONVST rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter a conversion phase. In this interface option, CONVST must remain high from the start of the conversion until all data bits are read. When started, the conversion continues regardless of the state of SCLK, however SCLK must be low at the CONVST rising edge.

ADS8866 ai_daisy_tim_v1_bas557.gifFigure 50. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode

At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 16-bit, shift register and also outputs the MSB bit of this conversion result on its own DOUT pin. All ADCs enter an acquisition phase and power-down. On every subsequent SCLK falling edge, the internal shift register of each ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT pin. Therefore, the digital host receives the data of ADC N, followed by the data of ADC N–1, and so on (in MSB-first fashion). A total of 16 x N SCLK falling edges are required to capture the outputs of all N devices in the chain. Data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame.