JAJSH04C May 2013 – March 2019 ADS8866
The application circuit is shown in Figure 52.
In such applications, the primary design requirement is to ensure that the full-scale step input signal settles to 16-bit accuracy at the ADC inputs. This condition is critical to achieve the excellent linearity specifications of the ADC. Therefore, the bandwidth of the charge-kickback RC filter must be large enough to allow optimal settling of the input signal during the ADC acquisition time. The filter capacitor helps reduce the sampling charge injection at the ADC inputs, but degrades the phase margin of the driving amplifier, thereby leading to stability issues. Amplifier stability is maintained by the series isolation resistor.
During the conversion process, binary-weighted capacitors are switched onto the REF pin. In order to support this dynamic load the output of the voltage reference must be buffered with a low-output impedance (high-bandwidth) buffer.
The REF60xx family of voltage references are able to maintain an output voltage within 1 LSB (16-bit) with minimal droop, even during the first conversion while driving the REF pin of the ADS8866. This feature is useful in burst-mode, event-triggered, equivalent-time sampling, and variable-sampling-rate data-acquisition systems.
For the input driving amplifiers, key specifications include rail-to-rail input and output swing, high bandwidth, high slew rate, and fast settling time. The CMOS amplifier meets all these specification requirements for this circuit with a single-supply and low quiescent current. The component values of the antialiasing filter are selected to meet the settling requirements of the system as well as to maintain the stability of the input driving amplifiers.