JAJSL61D february   2021  – june 2023 AFE7950

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3説明
  5. 4概要 (続き)
  6. 5Revision History
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Transmitter Electrical Characteristics
    6. 6.6  RF ADC Electrical Characteristics
    7. 6.7  PLL/VCO/Clock Electrical Characteristics
    8. 6.8  Digital Electrical Characteristics
    9. 6.9  Power Supply Electrical Characteristics
    10. 6.10 Timing Requirements
    11. 6.11 Switching Characteristics
    12. 6.12 Typical Characteristics
      1. 6.12.1  TX Typical Characteristics 800 MHz
      2. 6.12.2  TX Typical Characteristics at 1.8 GHz
      3. 6.12.3  TX Typical Characteristics at 2.6 GHz
      4. 6.12.4  TX Typical Characteristics at 3.5 GHz
      5. 6.12.5  TX Typical Characteristics at 4.9 GHz
      6. 6.12.6  TX Typical Characteristics at 8.1 GHz
      7. 6.12.7  TX Typical Characteristics at 9.6 GHz
      8. 6.12.8  RX Typical Characteristics at 800 MHz
      9. 6.12.9  RX Typical Characteristics at 1.75 GHz – 1.9 GHz
      10. 6.12.10 RX Typical Characteristics at 2.6 GHz
      11. 6.12.11 RX Typical Characteristics at 3.5 GHz
      12. 6.12.12 RX Typical Characteristics at 4.9 GHz
      13. 6.12.13 RX Typical Characteristics at 8.1GHz
      14. 6.12.14 RX Typical Characteristics at 9.6 GHz
      15. 6.12.15 PLL and Clock Typical Characteristics
  8. 7Device and Documentation Support
    1. 7.1 ドキュメントの更新通知を受け取る方法
    2. 7.2 サポート・リソース
    3. 7.3 商標
    4. 7.4 静電気放電に関する注意事項
    5. 7.5 用語集
  9. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.11 Switching Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TX Channel Latency
SerDes Receiver Analog Delay Full rate 2.8 ns
tJESDTX JESD to TX output Latency LMFSHd=2-8-8-1, 368.64 MSPS input rate, 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 152 interface clock cycles(1)
LMFSHd=8-16-4-1, 491.52 MSPS 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 176
LMFSHd=4-16-8-1, 245.76 MSPS 48x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 124
LMFSHd=2-16-16-1, 122.88 MSPS 96x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 97
RX Channel Latency
SerDes Transmitter Analog Delay 3.6 ns
tJESDRX RX input to JESD output Latency LMFS=2-16-16-1, 122.88 MSPS, 24x Decimation, Serdes rate = 16.22Gbps (JESD204C) 92 interface clock cycles(1)
LMFS=4-16-8-1, 245.76 MSPS, 12x Decimation, Serdes rate = 16.22Gbps (JESD204C) 108
LMFS=4-8-4-1, 491.52 MSPS, 6x Decimation, Serdes rate = 16.22Gbps (JESD204C) 153
FB Channel Latency
SerDes Transmitter Analog Delay 3.6 ns
tJESDFB FB input to JESD output Latency LMFS=1-2-8-1, 368.64 MSPS, 8x Decimation 151 interface clock cycles(1)
LMFS=2-4-4-1, 491.52 MSPS, 6x Decimation 177
(1) Interface clock cycles is the period of the digital interface sample rate, e.g. 1GSPS = 1ns.