JAJSGQ2F August   2013  – March 2019

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      充電器の効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Power Point Tracking
      2. 7.3.2 Battery Undervoltage Protection
      3. 7.3.3 Battery Overvoltage Protection
      4. 7.3.4 Battery Voltage in Operating Range (VBAT_OK Output)
      5. 7.3.5 Push-Pull Multiplexer Drivers
      6. 7.3.6 Nano-Power Management and Efficiency
    4. 7.4 Device Functional Modes
      1. 7.4.1 Main Boost Charger Disabled (Ship Mode) - (VSTOR > VSTOR_CHGEN and EN = HIGH)
      2. 7.4.2 Cold-Start Operation (VSTOR < VSTOR_CHGEN, VIN_DC > VIN(CS) and PIN > PIN(CS))
      3. 7.4.3 Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN, VIN_DC > VIN(DC) and EN = LOW )
      4. 7.4.4 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Energy Harvester Selection
      2. 8.1.2 Storage Element Selection
      3. 8.1.3 Inductor Selection
      4. 8.1.4 Capacitor Selection
        1. 8.1.4.1 VREF_SAMP Capacitance
        2. 8.1.4.2 VIN_DC Capacitance
        3. 8.1.4.3 VSTOR Capacitance
        4. 8.1.4.4 Additional Capacitance on VSTOR or VBAT_SEC
    2. 8.2 Typical Applications
      1. 8.2.1 Solar Application Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 TEG Application Circuit
      3. 8.2.3 Design Requirements
        1. 8.2.3.1 Detailed Design Procedure
        2. 8.2.3.2 Application Performance Plots
      4. 8.2.4 Piezoelectric Application Circuit
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 Zipファイル
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.4.3 Application Curves

bq25505 app3_startup_1VIN_8p5ma_100kohm_slusbj3.png
Sourcemeter with VSOURCE = 1.0 V and compliance of 8.5 mA subsequently applied to VIN_DC
VBAT_SEC = 0.1 F capacitor charged to 2.2 V
Resistance on VSTOR = 100 kΩ
Figure 35. Startup by Battery Attach With Partially Charged Storage Element
bq25505 app3_mppt_ov_3p3v_3vstor_2p0vin_42p6ma_slusbj3.png
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of 43 mA
VBAT_SEC = sourcemeter with VSOURCE = 3.0 V and compliance of 1 A
Figure 37. MPPT Operation
bq25505 app3_ov_3p3v_Vbatok_slusbj3.png
VIN_DC floating
No storage element on VBAT or VBAT_PRI
VSTOR artifically ramped from 0 V to 3.3 V to 0 V using a function generator
Figure 39. VBAT_OK Operation
bq25505 app3_operation_ov_3p3v_3vstor_2p0vin_42p6ma_slusbj3.png
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of 43 mA
VBAT_SEC = sourcemeter with VSOURCE = 3.0 V and compliance of 1 A
Figure 36. Boost Charger Operational Waveforms
bq25505 app3_ov_3p3v_VRDIV_slusbj3.png
VIN_DC = sourcemeter with VSOURCE = 2.0 V and compliance of 43 mA
VBAT_SEC = sourcemeter with VSOURCE = 3.0 V and compliance of 1 A
Figure 38. VRDIV Waveform