JAJSG05G November 2009 – November 2022 CDC3RL02
PRODUCTION DATA
Figure 9-1 shows the input stage of the CDC3RL02. The input signal at MCLK_IN can be a square wave or sine wave. CMCLK is an internal AC coupling capacitor that allows a direct connection from the TCXO to the CDC3RL02 without an external capacitor.
Any external component added in the series path of the clock signal will potentially add phase noise and jitter. The error source associated with the internal decoupling capacitor is included in the specification of the CDC3RL02. The recommended clock frequency band of the CDC3RL02 is 10 MHz to 80 MHz for specified functionality. All performance metrics are specified at 26 MHz. The lowest acceptable sinusoidal signal amplitude is 0.8 VPP for specified performance. Amplitudes as low as 0.3 VPP are acceptable but with reduced phase-noise and jitter performance.