SNAS811 July   2020  – May  CDCE6214

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Application Example CDCE6214
  4. 4 Revision History
  5. 5 Description (cont.)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions G = Ground, P = Power I = Input, I/O = Input/Output, O = Output I, RPUPD = Input with Resistive Pull-up and Pull-down I, RPU = Input with Resistive Pull=up I/O, RPU = Input/Output with resistive pull-up
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  EEPROM Characteristics
    6. 7.6  Reference Input, Single-Ended Characteristics
    7. 7.7  Reference Input, Differential Characteristics
    8. 7.8  Reference Input, Crystal Mode Characteristics
    9. 7.9  General-Purpose Input Characteristics
    10. 7.10 Triple Level Input Characteristics
    11. 7.11 Logic Output Characteristics
    12. 7.12 Phase Locked Loop Characteristics
    13. 7.13 Closed-Loop Output Jitter Characteristics
    14. 7.14 Input and Output Isolation
    15. 7.15 Buffer Mode Characteristics
    16. 7.16 PCIe Spread Spectrum Generator
    17. 7.17 LVCMOS Output Characteristics
    18. 7.18 LP-HCSL Output Characteristics
    19. 7.19 LVDS Output Characteristics
    20. 7.20 Output Synchronization Characteristics
    21. 7.21 Power-On Reset Characteristics
    22. 7.22 I2C-Compatible Serial Interface Characteristics
    23. 7.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 7.24 Power Supply Characteristics
    25. 7.25 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Reference Inputs
    2. 8.2 Outputs
    3. 8.3 Serial Interface
    4. 8.4 PSNR Test
    5. 8.5 Clock Interfacing and Termination
      1. 8.5.1 Reference Input
      2. 8.5.2 Outputs
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reference Block
        1. 9.3.1.1 Zero Delay Mode, Internal and External Path
      2. 9.3.2 Phase-Locked Loop (PLL)
        1. 9.3.2.1 PLL Configuration and Divider Settings
        2. 9.3.2.2 Spread Spectrum Clocking
        3. 9.3.2.3 Digitally-Controlled Oscillator/ Frequency Increment and Decrement - Serial Interface Mode and GPIO Mode
      3. 9.3.3 Clock Distribution
        1. 9.3.3.1 Glitchless Operation
        2. 9.3.3.2 Divider Synchronization
        3. 9.3.3.3 Global and Individual Output Enable
      4. 9.3.4 Power Supplies and Power Management
      5. 9.3.5 Control Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation Modes
        1. 9.4.1.1 Fall-Back Mode
        2. 9.4.1.2 Pin Mode
        3. 9.4.1.3 Serial Interface Mode
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Interface
      2. 9.5.2 EEPROM
        1. 9.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 9.5.2.2 Recommended Programming Procedure
        3. 9.5.2.3 EEPROM Access
          1. 9.5.2.3.1 Register Commit Flow
          2. 9.5.2.3.2 Direct Access Flow
        4. 9.5.2.4 Register Bits to EEPROM Mapping
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Sequence
    2. 11.2 Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
      2. 13.1.2 Device Nomenclature
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.5.2.4 Register Bits to EEPROM Mapping

Register bits settings are mapped into EEPROM. EEPROM is divided into three segments:

  • EEPROM Base Page: Selectable by connecting HW_SW_CTRL pin either to Logic 0 to Logic 1.
  • EEPROM Page 0: Selectable by connecting HW_SW_CTRL pin to Logic 0.
  • EEPROM Page 1: Selectable by connecting HW_SW_CTRL pin to Logic 1.

Table 21. EEPROM Mapping (20)(21)(22)(23)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 1 R5[8] R5[7] R5[6] R5[5] R5[4] R5[1] R4[3] R4[2] R4[1] R4[0] R3[9] R0[3]
1 0 1 0 0 1 0 0 0 0 1 1 1 1 1 R15[5] 1
2 0 0 0 1 1 0 1 1 0 0 0 1 0 0 1 0
3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 R48[4] R48[3] R48[2] R48[1] R48[0] R47[12] R47[11] R47[10] R47[9] R47[8] R47[7] 0 0 0 0 0
5 0 R49[4] R49[3] R49[2] R49[1] R49[0] R48[14] R48[13] R48[12] R48[11] R48[10] R48[9] R48[8] R48[7] R48[6] R48[5]
6 0 0 0 R50[10] R50[9] R50[8] 1 1 0 0 0 0 0 0 0 0
7 R55[6] R53[6] 1 R53[2] R53[1] R53[0] 1 0 1 0 0 0 0 0 0 0
8 1 0 0 0 0 0 1 R58[4] R58[3] R58[2] R58[1] R58[0] 0 R55[9] R55[8] R55[7]
9 0 1 R60[15] R60[14] R60[13] R60[12] R60[3] R60[2] R60[1] R60[0] R59[9] R59[8] R59[7] R59[6] R59[5] R59[4]
10 R65[8] R65[7] R65[6] R65[5] R65[4] 1 0 0 0 0 R64[9] R64[8] R64[7] R64[6] R64[5] 0
11 0 0 0 R69[9] R69[8] R69[7] R69[6] R69[5] 0 0 1 R66[3] R66[2] R66[1] R66[0] R65[9]
12 R74[5] 0 0 1 R71[3] R71[2] R71[1] R71[0] R70[9] R70[8] R70[7] R70[6] R70[5] R70[4] 1 0
13 R76[0] R75[9] R75[8] R75[7] R75[6] R75[5] R75[4] 1 0 0 0 0 R74[9] R74[8] R74[7] R74[6]
14 0 0 0 0 0 R79[3] R79[2] R79[1] R79[0] R76[9] R76[8] R76[7] R76[6] R76[3] R76[2] R76[1]
15 0 0 0 0 0 0 R81[3] 1 0 0 0 0 0 0 R80[3] 0
16 R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R0[15] R0[14] R0[13] R0[12] 0 R0[10] 0 R0[8] R0[0]
17 R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] R1[15] R1[14] R1[13] R1[12] R1[11] R1[10] R1[9] R1[8] R1[7]
18 0 R5[3] R5[2] R4[7] R4[6] R4[5] R4[4] R3[4] R3[3] R2[13] R2[12] R2[11] R2[10] R2[9] R2[8] R2[7]
19 R24[15] R24[12] R24[11] R24[10] R24[9] R24[8] 0 0 R24[5] R24[4] R24[3] R24[2] R24[1] R24[0] 0 0
20 R27[0] 0 R25[14] R25[13] R25[12] R25[11] R25[10] R25[9] R25[7] R25[6] R25[5] R25[4] R25[3] R25[2] R25[1] R25[0]
21 R30[14] R30[13] R30[12] R30[11] R30[10] R30[9] R30[8] R30[7] R30[6] R30[5] R30[4] R30[3] R30[2] R30[1] R30[0] R27[1]
22 R31[15] R31[14] R31[13] R31[12] R31[11] R31[10] R31[9] R31[8] R31[7] R31[6] R31[5] R31[4] R31[3] R31[2] R31[1] R31[0]
23 R33[7] R33[6] R33[5] R33[4] R33[3] R33[2] R33[1] R33[0] R32[7] R32[6] R32[5] R32[4] R32[3] R32[2] R32[1] R32[0]
24 R34[7] R34[6] R34[5] R34[4] R34[3] R34[2] R34[1] R34[0] R33[15] R33[14] R33[13] R33[12] R33[11] R33[10] R33[9] R33[8]
25 R43[10] R43[9] R43[8] R43[7] R43[6] R43[5] R43[4] R43[3] R43[2] R43[1] R43[0] R42[5] R42[3] R42[2] R42[1] R41[15]
26 R51[10] 0 0 1 R51[6] 0 0 R47[6] R47[5] R47[4] R47[3] R43[15] R43[14] R43[13] R43[12] R43[11]
27 R56[10] R56[9] R56[8] R56[7] R56[6] R56[5] R56[4] R56[3] R56[2] R56[1] R56[0] R53[3] 1 0 0 0
28 R57[14] R57[12] R57[9] R57[8] R57[7] R57[6] R57[5] R57[4] R57[3] R57[1] R57[0] R56[15] R56[14] R56[13] R56[12] R56[11]
29 R62[6] R62[5] R62[4] R62[3] R62[2] R62[1] R62[0] R60[11] R60[10] R60[5] R60[4] R59[15] R59[14] R59[13] R59[12] R59[11]
30 R63[7] R63[6] R63[5] R63[4] R63[3] R63[1] R63[0] R62[15] R62[14] R62[13] R62[12] R62[11] R62[10] R62[9] R62[8] R62[7]
31 R67[6] R67[5] R67[4] R67[3] R67[2] R67[1] R67[0] R66[5] R66[4] R65[14] R65[13] R65[11] R63[13] R63[12] R63[9] R63[8]
32 R68[7] R68[6] R68[5] R68[4] R68[3] R68[1] R68[0] R67[15] R67[14] R67[13] R67[12] R67[11] R67[10] R67[9] R67[8] R67[7]
33 R72[6] R72[5] R72[4] R72[3] R72[2] R72[1] R72[0] R71[10] R71[9] R71[5] R71[4] R70[11] R68[13] R68[12] R68[9] R68[8]
34 R73[7] R73[6] R73[5] R73[4] R73[3] R73[1] R73[0] R72[15] R72[14] R72[13] R72[12] R72[11] R72[10] R72[9] R72[8] R72[7]
35 0 0 0 R77[1] R77[0] R76[5] R76[4] R75[15] R75[14] R75[13] R75[12] R75[11] R73[13] R73[12] R73[9] R73[8]
36 0 0 0 0 0 0 0 0 0 R79[9] R78[12] 0 0 0 0 0
37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
39 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
40 R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] R0[15] R0[14] R0[13] R0[12] 0 R0[10] 0 R0[8] R0[0]
41 R2[6] R2[5] R2[4] R2[3] R2[2] R2[1] R2[0] R1[15] R1[14] R1[13] R1[12] R1[11] R1[10] R1[9] R1[8] R1[7]
42 0 R5[3] R5[2] R4[7] R4[6] R4[5] R4[4] R3[4] R3[3] R2[13] R2[12] R2[11] R2[10] R2[9] R2[8] R2[7]
43 R24[15] R24[12] R24[11] R24[10] R24[9] R24[8] 0 0 R24[5] R24[4] R24[3] R24[2] R24[1] R24[0] 0 0
44 R27[0] 0 R25[14] R25[13] R25[12] R25[11] R25[10] R25[9] R25[7] R25[6] R25[5] R25[4] R25[3] R25[2] R25[1] R25[0]
45 R30[14] R30[13] R30[12] R30[11] R30[10] R30[9] R30[8] R30[7] R30[6] R30[5] R30[4] R30[3] R30[2] R30[1] R30[0] R27[1]
46 R31[15] R31[14] R31[13] R31[12] R31[11] R31[10] R31[9] R31[8] R31[7] R31[6] R31[5] R31[4] R31[3] R31[2] R31[1] R31[0]
47 R33[7] R33[6] R33[5] R33[4] R33[3] R33[2] R33[1] R33[0] R32[7] R32[6] R32[5] R32[4] R32[3] R32[2] R32[1] R32[0]
48 R34[7] R34[6] R34[5] R34[4] R34[3] R34[2] R34[1] R34[0] R33[15] R33[14] R33[13] R33[12] R33[11] R33[10] R33[9] R33[8]
49 R43[10] R43[9] R43[8] R43[7] R43[6] R43[5] R43[4] R43[3] R43[2] R43[1] R43[0] R42[5] R42[3] R42[2] R42[1] R41[15]
50 R51[10] 0 0 1 R51[6] 0 0 R47[6] R47[5] R47[4] R47[3] R43[15] R43[14] R43[13] R43[12] R43[11]
51 R56[10] R56[9] R56[8] R56[7] R56[6] R56[5] R56[4] R56[3] R56[2] R56[1] R56[0] R53[3] 1 0 0 0
52 R57[14] R57[12] R57[9] R57[8] R57[7] R57[6] R57[5] R57[4] R57[3] R57[1] R57[0] R56[15] R56[14] R56[13] R56[12] R56[11]
53 R62[6] R62[5] R62[4] R62[3] R62[2] R62[1] R62[0] R60[11] R60[10] R60[5] R60[4] R59[15] R59[14] R59[13] R59[12] R59[11]
54 R63[7] R63[6] R63[5] R63[4] R63[3] R63[1] R63[0] R62[15] R62[14] R62[13] R62[12] R62[11] R62[10] R62[9] R62[8] R62[7]
55 R67[6] R67[5] R67[4] R67[3] R67[2] R67[1] R67[0] R66[5] R66[4] R65[14] R65[13] R65[11] R63[13] R63[12] R63[9] R63[8]
56 R68[7] R68[6] R68[5] R68[4] R68[3] R68[1] R68[0] R67[15] R67[14] R67[13] R67[12] R67[11] R67[10] R67[9] R67[8] R67[7]
57 R72[6] R72[5] R72[4] R72[3] R72[2] R72[1] R72[0] R71[10] R71[9] R71[5] R71[4] R70[11] R68[13] R68[12] R68[9] R68[8]
58 R73[7] R73[6] R73[5] R73[4] R73[3] R73[1] R73[0] R72[15] R72[14] R72[13] R72[12] R72[11] R72[10] R72[9] R72[8] R72[7]
59 0 0 0 R77[1] R77[0] R76[5] R76[4] R75[15] R75[14] R75[13] R75[12] R75[11] R73[13] R73[12] R73[9] R73[8]
60 0 0 0 0 0 0 0 0 0 R79[9] R78[12] 0 0 0 0 0
61 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
62 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
63 SCRC[15] SCRC[14] SCRC[13] SCRC[12] SCRC[11] SCRC[10] SCRC[9] SCRC[8] SCRC[7] SCRC[6] SCRC[5] SCRC[4] SCRC[3] SCRC[2] SCRC[1] SCRC[0]
20. Address Locations 0-15: EEPROM Base Page
21. Address Locations 16-39: EEPROM Page 0
22. Address Locations 40-63: EEPROM Page 1
23. Bit locations marked in Red may vary from device to device

Table 22. Register Defaults in Fall-Back Mode and EEPROM Mode

REGISTER ADDRESSES FALL-BACK MODE HW_SW_CTRL = 0 HW_SW_CTRL = 1 REGISTER ADDRESSES FALL-BACK MODE HW_SW_CTRL = 0 HW_SW_CTRL = 1
R85 x0000 x0000 x0000 R42 x0002 x0002 x0002
R84 x0000 x0000 x0000 R41 x0000 x0000 x0000
R83 x0000 xFF00 xFF00 R40 x0000 x0000 x0000
R82 x0000 x01C0 x01C0 R39 x0000 x0000 x0000
R81 x0004 x0004 x0004 R38 x0000 x0000 x0000
R80 x0000 x0008 x0008 R37 x0000 x0000 x0000
R79 x0008 x0008 x0008 R36 x0000 x0000 x0000
R78 x1000 x0000 x0000 R35 x0000 x0028 x0028
R77 x0000 x0002 x0002 R34 x0000 x0000 x0000
R76 x0008 x0188 x0188 R33 x0000 x0000 x0000
R75 x0008 x0008 x8008 R32 x0000 x0000 x0000
R74 xA181 xA181 xA181 R31 x0000 x0000 x0000
R73 x2000 x2000 x0000 R30 x0030 x0030 x0030
R72 x0006 x0006 x0006 R29 x0000 x0000 x0000
R71 x0000 x0406 x0406 R28 x0000 x0000 x0000
R70 x0008 x0008 x0808 R27 x0005 x0004 x0004
R69 xA181 xA181 xA181 R26 x0000 x0000 x0000
R68 x2000 x2000 x0000 R25 x0400 x0400 x0400
R67 x0006 x0006 x0006 R24 x0718 x091C x091C
R66 x0000 x0006 x0006 R23 x0000 x2406 x2406
R65 x0008 x4008 x4808 R22 x06A2 x06A2 x06A2
R64 xA181 xA181 xA181 R21 x0000 x0590 x0513
R63 x2000 x2000 x0000 R20 x0000 x0000 x0000
R62 x0006 x0006 x0006 R19 x0000 x0000 x0000
R61 x0000 x0000 x0000 R18 x0000 x0000 x0000
R60 x0008 x0008 x6028 R17 x26C4 x26C4 x26C4
R59 x0008 x0008 x8008 R16 x921F x921F x921F
R58 x502C x502C x502C R15 xA037 xA037 xA037
R57 x4000 x4000 x0000 R14 x0000 x0000 x0000
R56 x0006 x0006 x0006 R13 x0000 x0000 x0000
R55 x001E x001E x001E R12 x0000 x0000 x7002
R54 x3400 x3400 x3400 R11 x0000 x0000 x003F
R53 x0069 x0069 x0069 R10 x0000 xA777 xA777
R52 x5000 x5000 x5000 R9 x0000 x7BFA xA777
R51 x40C0 x40C0 x40C0 R8 x0000 x0001 x0001
R50 x01C0 x01C0 x01C0 R7 x0000 x0C2D x0C0D
R49 x0013 x0013 x0013 R6 x0000 x0E6C x0E6C
R48 x1A14 x1A05 x1A05 R5 x0008 x0008 x0008
R47 x0A00 x0280 x0280 R4 x0000 x0000 x0000
R46 x0000 x0000 x0000 R3 x0000 x0200 x0200
R45 x4F80 x4F80 x4F80 R2 x0000 x0000 x0000
R44 x0318 x0318 x0318 R1 x2310 x7654 x7652
R43 x0051 x0051 x0051 R0 x0000 x0001 x2000