JAJSH89D May   2012  – April 2019 CDCUN1208LP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ピン構成の概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode
    6. 6.6  Universal Input (IN1, IN2) Characteristics
    7. 6.7  Clock Output Buffer Characteristics (Output Mode = LVDS)
    8. 6.8  Clock Output Buffer Characteristics (Output Mode = HCSL)
    9. 6.9  Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
    10. 6.10 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    11. 6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Device Control Using Configuration Pins
        1. 8.3.1.1 Configuration of Output Type (OTTP)
        2. 8.3.1.2 Configuration of Edge Rate Control (ERC)
        3. 8.3.1.3 Control of Output Enable (OE)
      2. 8.3.2 Input Ports (IN1, IN2)
        1. 8.3.2.1 Configuration of the Input Type (ITTP)
        2. 8.3.2.2 Configuration of the IN2 Divider (INDIV)
      3. 8.3.3 Smart Input Multiplexer (INMUX)
        1. 8.3.3.1 Pin Configuration of the Smart Input Multiplexer (INMUX)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Control Using the Host Interface
        1. 8.4.1.1 OE and INSEL in Host Configuration Mode
    5. 8.5 Programming
      1. 8.5.1 Host Interface Hardware Information
        1. 8.5.1.1 SPI Communication
          1. 8.5.1.1.1 CDCUN1208LP SPI Addressing
          2. 8.5.1.1.2 Writing to the CDCUN1208LP
          3. 8.5.1.1.3 Reading From the CDCUN1208LP
          4. 8.5.1.1.4 Block Write/Read Operation
        2. 8.5.1.2 I2C Communication
          1. 8.5.1.2.1 Message Transmission
            1. 8.5.1.2.1.1 Data and Address Bits
            2. 8.5.1.2.1.2 Special Symbols – Start (S) and Stop (P)
            3. 8.5.1.2.1.3 Special Symbols – Acknowledge (ACK)
            4. 8.5.1.2.1.4 Generic Message Frame
            5. 8.5.1.2.1.5 CDCUN1208LP Message Format
            6. 8.5.1.2.1.6 CDCUN1208LP Device Addressing (I2C Address)
            7. 8.5.1.2.1.7 CDCUN1208LP Device Addressing (Register Address)
          2. 8.5.1.2.2 I2C Master and Slave Handshaking
          3. 8.5.1.2.3 Block Read/Write
          4. 8.5.1.2.4 I2C Timing
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers
        1. 8.6.1.1 Device Registers: Register 00-07
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 PCI Express Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
  10. 10Power Supply Recommendations
    1. 10.1 CDCUN1208LP Power Consumption
    2. 10.2 Device Power Supply Connections and Sequencing
    3. 10.3 Device Inputs (IN1, IN2)
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1.1 OE and INSEL in Host Configuration Mode

In host configuration mode, the OE pin is no longer available; thus buffers are controlled individually through the host interface. The input multiplexer can be controlled either through the pin or through the device registers, in accordance with Table 12.

CDCUN1208LP host_conf_cas928.gifFigure 30. CDCUN1208LP Host Configuration – Typical Application

When the host interface is enabled, certain pins take on alternative functions, according to Table 8.

Table 8. CDCUN1208LP Host Configuration Pins

PIN NAME IN
HOST MODE		 ALT PIN NAME IN PIN MODE (MODE = OPEN) PIN
NUMBER		 PIN NAME IN HOST PROGRAMMING MODE
(MODE/Pin 30 is tied high or low)		 PIN NAME IN PIN CONFIGURATION MODE
(only if MODE/Pin 30 is OPEN)
MODE 30 Programming mode
1 = I2C, 0 = SPI,OPEN = Pins (alternative description applies)
SDA/MOSI DIVIDE 1 Host interface data (I2C) / SPI Master output slave input (data In) Input divider pin control
MISO OTTP 19 SPI master input slave output (data out) Output type (OTTP) pin control
SCL OE 32 Host interface clock Device output enable
1 = Enable, 0 = Disable
ADDR/CS ERC 31 Host interface address (I2C) / chip select (SPI)
Pull ADDR to GND for I2C communication 		Output edge rate control
1 = Fast, 0 = Slow, OPEN = Medium

The CDCUN1208LP samples the MODE pin after the device exits the power-on reset (POR) state. The device is placed in the RESET state in one of two ways: a POR circuit automatically resets the device after power is applied; or through the RESET bit (R15[1]) in register memory (see Table 12). This RESET bit is only accessible in host configuration mode. If the MODE pin (pin 11) is open (no connection), then the device is placed in the pin configuration mode and all settings are determined by the state of various pins according to Table 1 and Figure 28. If the MODE pin is low, then device enables the SPI interface; and, if MODE is high, then I2C is enabled.

CDCUN1208LP pin_host_conf_cas928.gifFigure 31. CDCUN1208LP Pin and Host Configuration Mode