JAJSGU1B January 2019 – May 2022 DLP4500NIR
The DLPC350 controller provides two external program memory chip selects:
The flash access timing is fixed at 100.5 ns for read timing, and 154.1 ns for write timing. In standby mode, these values change to 803.5 ns for read timing and 1232.1 ns for write timing.
These timing values assume a maximum single direction trace length of 75 mm. When an additional flash is used in conjunction with the boot flash, stub lengths must be kept short and located as close as possible to the flash end of the route.
The DLPC350 controller provides enough program memory address pins to support a flash device up to 128 Mb. PM_ADDR_22 and PM_ADDR_21 are tri-stated GPIO pins during reset, so they require board-level pulldown resistors to prevent the flash address bits from floating during initial bootload.