JAJSGU1B January 2019 – May 2022 DLP4500NIR
The DLPC350 PCB is targeted at six layers with layer stack up shown in Figure 11-2. The PCB layer stack may vary depending on system design. However, careful attention is required to meet design considerations. Layers one and six should consist of the components layers. Low-speed routing and power splits are allowed on these layers. Layer two should consist of a solid ground plane. Layer five should be a split voltage plane. Layers three and four should be used as the primary routing layers. Routing on external layers should be less than 0.25 inches for priority one and two signals. Refer to Table 11-7 for signal priority groups.
Board material should be FR-370HR or similar. PCB should be designed for lead-free assembly with the stackup geometry shown in Figure 11-2.
|Reference plane 1||Ground plane for proper return|
|Reference plane 2||1.9-V DMD I/O power plane or ground|
|Er||Dielectric FR4||4.3 at 1 GHz (nominal)|
|H1||Signal trace distance to reference plane 1||5 mil (0.127 mm)|
|H2||Signal trace distance to reference plane 2||30.4 mil|