JAJSLA9E may 2015 – april 2023 DLP7000UV
PRODUCTION DATA
PIN (1) | TYPE (I/O/P) |
SIGNAL | DATA RATE (2) | INTERNAL TERM (3) | CLOCK | DESCRIPTION | TRACE (MILS) | |
---|---|---|---|---|---|---|---|---|
NAME | NO. | |||||||
DATA INPUT | ||||||||
D_AN(0) | B10 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 368.72 | |
D_AN(1) | A13 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 424.61 | |
D_AN(2) | D16 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 433.87 | |
D_AN(3) | C17 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 391.39 | |
D_AN(4) | B18 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 438.57 | |
D_AN(5) | A17 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 391.13 | |
D_AN(6) | A25 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 563.26 | |
D_AN(7) | D22 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 411.62 | |
D_AN(8) | C29 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | Input data bus A (2x LVDS) | 595.11 |
D_AN(9) | D28 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 543.07 | |
D_AN(10) | E27 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 455.98 | |
D_AN(11) | F26 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 359.5 | |
D_AN(12) | G29 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 542.67 | |
D_AN(13) | H28 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 551.51 | |
D_AN(14) | J27 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 528.04 | |
D_AN(15) | K26 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 484.38 | |
D_AP(0) | B12 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 366.99 | |
D_AP(1) | A11 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 417.47 | |
D_AP(2) | D14 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 434.89 | |
D_AP(3) | C15 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 394.67 | |
D_AP(4) | B16 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 437.3 | |
D_AP(5) | A19 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 389.01 | |
D_AP(6) | A23 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 562.92 | |
D_AP(7) | D20 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 410.34 | |
D_AP(8) | A29 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 594.61 | |
D_AP(9) | B28 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 539.88 | |
D_AP(10) | C27 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 456.78 | |
D_AP(11) | D26 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 360.68 | |
D_AP(12) | F30 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | Input data bus A (2x LVDS) | 543.97 |
D_AP(13) | H30 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 570.85 | |
D_AP(14) | J29 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 527.18 | |
D_AP(15) | K28 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 481.02 | |
D_BN(0) | AB10 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 368.72 | |
D_BN(1) | AC13 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 424.61 | |
D_BN(2) | Y16 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 433.87 | |
D_BN(3) | AA17 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 391.39 | |
D_BN(4) | AB18 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 438.57 | |
D_BN(5) | AC17 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 391.13 | |
D_BN(6) | AC25 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 563.26 | |
D_BN(7) | Y22 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 411.62 | |
D_BN(8) | AA29 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 595.11 | |
D_BN(9) | Y28 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 543.07 | |
D_BN(10) | W27 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 455.98 | |
D_BN(11) | V26 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 360.94 | |
D_BN(12) | T30 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 575.85 | |
D_BN(13) | R29 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 519.37 | |
D_BN(14) | R27 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 532.59 | |
D_BN(15) | N27 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 441.14 | |
D_BP(0) | AB12 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 366.99 | |
D_BP(1) | AC11 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 417.47 | |
D_BP(2) | Y14 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 434.89 | |
D_BP(3) | AA15 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 394.67 | |
D_BP(4) | AB16 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 437.3 | |
D_BP(5) | AC19 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 389.01 | |
D_BP(6) | AC23 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | Input data bus B (2x LVDS) Input data bus B (2x LVDS) | 562.92 |
D_BP(7) | Y20 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 410.34 | |
D_BP(8) | AC29 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 594.61 | |
D_BP(9) | AB28 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 539.88 | |
D_BP(10) | AA27 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 456.78 | |
D_BP(11) | Y26 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 360.68 | |
D_BP(12) | U29 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 578.46 | |
D_BP(13) | T28 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 509.74 | |
D_BP(14) | P28 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | Input data bus B (2x LVDS) | 534.59 |
D_BP(15) | P26 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 440 | |
DATA CLOCK | ||||||||
DCLK_AN | B22 | Input | LVCMOS | – | Differential Terminated - 100 Ω | – | 477.10 | |
DCLK_AP | B24 | Input | LVCMOS | – | Differential Terminated - 100 Ω | – | 477.11 | |
DCLK_BN | AB22 | Input | LVCMOS | – | Differential Terminated - 100 Ω | – | 477.10 | |
DCLK_BP | AB24 | Input | LVCMOS | – | Differential Terminated - 100 Ω | – | 477.11 | |
DATA CONTROL INPUTS | ||||||||
SCTRL_AN | C21 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | Serial control for data bus A (2x LVDS) | 477.07 |
SCTRL_AP | C23 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_A | 477.14 | |
SCTRL_BN | AA21 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | Serial control for data bus B (2x LVDS) | 477.07 |
SCTRL_BP | AA23 | Input | LVCMOS | DDR | Differential Terminated - 100 Ω | DCLK_B | 477.14 | |
SERIAL COMMUNICATION AND CONFIGURATION | ||||||||
SCPCLK | E3 | Input | LVCMOS | – | Pull-down | – | Serial port clock | 379.29 |
SCPDO | B2 | Output | LVCMOS | – | – | SCPCLK | Serial port output | 480.91 |
SCPDI | F4 | Input | LVCMOS | – | Pull-down | SCPCLK | Serial port input | 323.56 |
SCPENZ | D4 | Input | LVCMOS | – | Pull-down | SCPCLK | Serial port enable | 326.99 |
PWRDNZ | C3 | Input | LVCMOS | – | Pull-down | – | Device Reset | 406.28 |
MODE_A | D8 | Input | LVCMOS | – | Pull-down | – | Data bandwidth mode select | 396.05 |
MODE_B | C11 | Input | LVCMOS | – | Pull-down | – | 208.86 | |
MICROMIRROR BIAS CLOCKING PULSE | ||||||||
MBRST(0) | P2 | Input | Analog | – | – | – | ||
MBRST(1) | AB4 | Input | Analog | – | – | – | ||
MBRST(2) | AA7 | Input | Analog | – | – | – | ||
MBRST(3) | N3 | Input | Analog | – | – | – | ||
MBRST(4) | M4 | Input | Analog | – | – | – | ||
MBRST(5) | AB6 | Input | Analog | – | – | – | ||
MBRST(6) | AA5 | Input | Analog | – | – | – | ||
MBRST(7) | L3 | Input | Analog | – | – | – | Micromirror Bias Clocking Pulse MBRST signals clock micromirrors into state of LVCMOS memory cell associated with each mirror. | |
MBRST(8) | Y6 | Input | Analog | – | – | – | ||
MBRST(9) | K4 | Input | Analog | – | – | – | ||
MBRST(10) | L5 | Input | Analog | – | – | – | ||
MBRST(11) | AC5 | Input | Analog | – | – | – | ||
MBRST(12) | Y8 | Input | Analog | – | – | – | ||
MBRST(13) | J5 | Input | Analog | – | – | – | ||
MBRST(14) | K6 | Input | Analog | – | – | – | ||
MBRST(15) | AC7 | Input | Analog | – | – | – | ||
POWER | ||||||||
VCC | A7, A15, C1, E1, U1, W1, AB2,AC9, AC15 | Power | Analog | – | – | – | Power for LVCMOS Logic | – |
VCC1 | A21, A27, D30, M30, Y30, AC21, AC27 | Power | Analog | – | – | – | Power supply for LVDS Interface | – |
VCC2 | G1, J1, L1, N1, R1 | Power | Analog | – | – | – | Power for High Voltage CMOS Logic | – |
VSS | A1, A3, A5, A9, B4, B8, B14, B20, B26, B30, C7, | Power | Analog | – | – | – | Common return for all power inputs | – |
C13, C19, C25, D6, D12, D18, D24, E29, F2, F28, | ||||||||
G3, G27, H2, H4, H26, J3, J25 ,K2, K30, L25, | ||||||||
L27, L29, M2, M6, M26, M28, N5, N25, N29, P4, | ||||||||
P30, R3, R5, R25, T2, T26, U27, V28, V30, W5, | ||||||||
W29, Y4, Y12, Y18, Y24, AA3,AA9, AA13, AA19, | ||||||||
AA25, AB8, AB14, AB20, AB26, AB30 | ||||||||
RESERVED SIGNALS (NOT FOR USE IN SYSTEM) | ||||||||
RESERVED_AA1 | AA1 | Input | LVCMOS | – | Pull-down | – | Pins should be connected to VSS | – |
RESERVED_B6 | B6 | Input | LVCMOS | – | Pull-down | – | – | – |
RESERVED_T4 | T4 | Input | LVCMOS | – | Pull-down | – | – | – |
RESERVED_U5 | U5 | Input | LVCMOS | – | Pull-down | – | – | – |
NO_CONNECT | AA11, AC3, C5, C9, D10, D2, E5,G5, H6, P6, T6, | – | – | – | – | – | DO NOT CONNECT | – |
U3, V2, V4, W3, Y10, Y2 |