JAJSD08D October   2015  – November 2022 DP83867CS , DP83867E , DP83867IS

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1. 6.1 Pin Functions
    2. 6.2 Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power-Up Timing
    7. 7.7  Reset Timing
    8. 7.8  MII Serial Management Timing
    9. 7.9  SGMII Timing
    10. 7.10 RGMII Timing
    11. 7.11 DP83867E Start of Frame Detection Timing
    12. 7.12 DP83867IS/CS Start of Frame Detection Timing
    13. 7.13 Timing Diagrams
    14. 7.14 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 8.3.1.1 Magic Packet Structure
        2. 8.3.1.2 Magic Packet Example
        3. 8.3.1.3 Wake-on-LAN Configuration and Status
      2. 8.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 8.3.2.1 SFD Latency Variation and Determinism
          1. 8.3.2.1.1 1000-Mb SFD Variation in Master Mode
          2. 8.3.2.1.2 1000-Mb SFD Variation in Slave Mode
          3. 8.3.2.1.3 100-Mb SFD Variation
      3. 8.3.3 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 MAC Interfaces
        1. 8.4.1.1 Serial GMII (SGMII)
        2. 8.4.1.2 Reduced GMII (RGMII)
          1. 8.4.1.2.1 1000-Mbps Mode Operation
          2. 8.4.1.2.2 1000-Mbps Mode Timing
          3. 8.4.1.2.3 10- and 100-Mbps Mode
      2. 8.4.2 Serial Management Interface
        1. 8.4.2.1 Extended Address Space Access
          1. 8.4.2.1.1 Write Address Operation
          2. 8.4.2.1.2 Read Address Operation
          3. 8.4.2.1.3 Write (No Post Increment) Operation
          4. 8.4.2.1.4 Read (No Post Increment) Operation
          5. 8.4.2.1.5 Write (Post Increment) Operation
          6. 8.4.2.1.6 Read (Post Increment) Operation
          7. 8.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 8.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 8.4.3 Auto-Negotiation
        1. 8.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 8.4.3.2 Master and Slave Resolution
        3. 8.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 8.4.3.4 Next Page Support
        5. 8.4.3.5 Parallel Detection
        6. 8.4.3.6 Restart Auto-Negotiation
        7. 8.4.3.7 Enabling Auto-Negotiation Through Software
        8. 8.4.3.8 Auto-Negotiation Complete Time
        9. 8.4.3.9 Auto-MDIX Resolution
      4. 8.4.4 Loopback Mode
        1. 8.4.4.1 Near-End Loopback
          1. 8.4.4.1.1 MII Loopback
          2. 8.4.4.1.2 PCS Loopback
          3. 8.4.4.1.3 Digital Loopback
          4. 8.4.4.1.4 Analog Loopback
        2. 8.4.4.2 External Loopback
        3. 8.4.4.3 Far-End (Reverse) Loopback
      5. 8.4.5 BIST Configuration
      6. 8.4.6 Cable Diagnostics
        1. 8.4.6.1 TDR
        2. 8.4.6.2 Energy Detect
        3. 8.4.6.3 Fast Link Detect
        4. 8.4.6.4 Speed Optimization
        5. 8.4.6.5 Mirror Mode
        6. 8.4.6.6 Interrupt
        7. 8.4.6.7 IEEE 802.3 Test Modes
    5. 8.5 Programming
      1. 8.5.1 Strap Configuration
      2. 8.5.2 LED Configuration
      3. 8.5.3 LED Operation From 1.8-V I/O VDD Supply
      4. 8.5.4 PHY Address Configuration
      5. 8.5.5 Reset Operation
        1. 8.5.5.1 Hardware Reset
        2. 8.5.5.2 IEEE Software Reset
        3. 8.5.5.3 Global Software Reset
        4. 8.5.5.4 Global Software Restart
        5. 8.5.5.5 PCS Restart
      6. 8.5.6 Power-Saving Modes
        1. 8.5.6.1 IEEE Power Down
        2. 8.5.6.2 Deep Power-Down Mode
        3. 8.5.6.3 Active Sleep
        4. 8.5.6.4 Passive Sleep
    6. 8.6 Register Maps
      1. 8.6.1   Basic Mode Control Register (BMCR)
      2. 8.6.2   Basic Mode Status Register (BMSR)
      3. 8.6.3   PHY Identifier Register #1 (PHYIDR1)
      4. 8.6.4   PHY Identifier Register #2 (PHYIDR2)
      5. 8.6.5   Auto-Negotiation Advertisement Register (ANAR)
      6. 8.6.6   Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.6.7   Auto-Negotiate Expansion Register (ANER)
      8. 8.6.8   Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 8.6.9   Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 8.6.10  1000BASE-T Configuration Register (CFG1)
      11. 8.6.11  Status Register 1 (STS1)
      12. 8.6.12  Extended Register Addressing
        1. 8.6.12.1 Register Control Register (REGCR)
        2. 8.6.12.2 Address or Data Register (ADDAR)
      13. 8.6.13  1000BASE-T Status Register (1KSCR)
      14. 8.6.14  PHY Control Register (PHYCR)
      15. 8.6.15  PHY Status Register (PHYSTS)
      16. 8.6.16  MII Interrupt Control Register (MICR)
      17. 8.6.17  Interrupt Status Register (ISR)
      18. 8.6.18  Configuration Register 2 (CFG2)
      19. 8.6.19  Receiver Error Counter Register (RECR)
      20. 8.6.20  BIST Control Register (BISCR)
      21. 8.6.21  Status Register 2 (STS2)
      22. 8.6.22  LED Configuration Register 1 (LEDCR1)
      23. 8.6.23  LED Configuration Register 2 (LEDCR2)
      24. 8.6.24  LED Configuration Register (LEDCR3)
      25. 8.6.25  Configuration Register 3 (CFG3)
      26. 8.6.26  Control Register (CTRL)
      27. 8.6.27  Testmode Channel Control (TMCH_CTRL)
      28. 8.6.28  Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)
      29. 8.6.29  Fast Link Drop Configuration Register (FLD_CFG)
      30. 8.6.30  Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)
      31. 8.6.31  Configuration Register 4 (CFG4)
      32. 8.6.32  RGMII Control Register (RGMIICTL)
      33. 8.6.33  RGMII Control Register 2 (RGMIICTL2)
      34. 8.6.34  SGMII Auto-Negotiation Status (SGMII_ANEG_STS)
      35. 8.6.35  100BASE-TX Configuration (100CR)
      36. 8.6.36  Viterbi Module Configuration (VTM_CFG)
      37. 8.6.37  Skew FIFO Status (SKEW_FIFO)
      38. 8.6.38  Strap Configuration Status Register 1 (STRAP_STS1)
      39. 8.6.39  Strap Configuration Status Register 2 (STRAP_STS2)
      40. 8.6.40  BIST Control and Status Register 1 (BICSR1)
      41. 8.6.41  BIST Control and Status Register 2 (BICSR2)
      42. 8.6.42  BIST Control and Status Register 3 (BICSR3)
      43. 8.6.43  BIST Control and Status Register 4 (BICSR4)
      44. 8.6.44  Configuration for Receiver's Equalizer (CRE)
      45. 8.6.45  RGMII Delay Control Register (RGMIIDCTL)
      46. 8.6.46  Configuration of Receiver's LPF (CRLPF)
      47. 8.6.47  Enable Control of Receiver's Equalizer (ECRE)
      48. 8.6.48  PLL Clock-out Control Register (PLLCTL)
      49. 8.6.49  SGMII Control Register 1 (SGMIICTL1)
      50. 8.6.50  Sync FIFO Control (SYNC_FIFO_CTRL)
      51. 8.6.51  Loopback Configuration Register (LOOPCR)
      52. 8.6.52  DSP Configuration (DSP_CONFIG)
      53. 8.6.53  DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)
      54. 8.6.54  Receive Configuration Register (RXFCFG)
      55. 8.6.55  Receive Status Register (RXFSTS)
      56. 8.6.56  Pattern Match Data Register 1 (RXFPMD1)
      57. 8.6.57  Pattern Match Data Register 2 (RXFPMD2)
      58. 8.6.58  Pattern Match Data Register 3 (RXFPMD3)
      59. 8.6.59  SecureOn Pass Register 2 (RXFSOP1)
      60. 8.6.60  SecureOn Pass Register 2 (RXFSOP2)
      61. 8.6.61  SecureOn Pass Register 3 (RXFSOP3)
      62. 8.6.62  Receive Pattern Register 1 (RXFPAT1)
      63. 8.6.63  Receive Pattern Register 2 (RXFPAT2)
      64. 8.6.64  Receive Pattern Register 3 (RXFPAT3)
      65. 8.6.65  Receive Pattern Register 4 (RXFPAT4)
      66. 8.6.66  Receive Pattern Register 5 (RXFPAT5)
      67. 8.6.67  Receive Pattern Register 6 (RXFPAT6)
      68. 8.6.68  Receive Pattern Register 7 (RXFPAT7)
      69. 8.6.69  Receive Pattern Register 8 (RXFPAT8)
      70. 8.6.70  Receive Pattern Register 9 (RXFPAT9)
      71. 8.6.71  Receive Pattern Register 10 (RXFPAT10)
      72. 8.6.72  Receive Pattern Register 11 (RXFPAT11)
      73. 8.6.73  Receive Pattern Register 12 (RXFPAT12)
      74. 8.6.74  Receive Pattern Register 13 (RXFPAT13)
      75. 8.6.75  Receive Pattern Register 14 (RXFPAT14)
      76. 8.6.76  Receive Pattern Register 15 (RXFPAT15)
      77. 8.6.77  Receive Pattern Register 16 (RXFPAT16)
      78. 8.6.78  Receive Pattern Register 17 (RXFPAT17)
      79. 8.6.79  Receive Pattern Register 18 (RXFPAT18)
      80. 8.6.80  Receive Pattern Register 19 (RXFPAT19)
      81. 8.6.81  Receive Pattern Register 20 (RXFPAT20)
      82. 8.6.82  Receive Pattern Register 21 (RXFPAT21)
      83. 8.6.83  Receive Pattern Register 22 (RXFPAT22)
      84. 8.6.84  Receive Pattern Register 23 (RXFPAT23)
      85. 8.6.85  Receive Pattern Register 24 (RXFPAT24)
      86. 8.6.86  Receive Pattern Register 25 (RXFPAT25)
      87. 8.6.87  Receive Pattern Register 26 (RXFPAT26)
      88. 8.6.88  Receive Pattern Register 27 (RXFPAT27)
      89. 8.6.89  Receive Pattern Register 28 (RXFPAT28)
      90. 8.6.90  Receive Pattern Register 29 (RXFPAT29)
      91. 8.6.91  Receive Pattern Register 30 (RXFPAT30)
      92. 8.6.92  Receive Pattern Register 31 (RXFPAT31)
      93. 8.6.93  Receive Pattern Register 32 (RXFPAT32)
      94. 8.6.94  Receive Pattern Byte Mask Register 1 (RXFPBM1)
      95. 8.6.95  Receive Pattern Byte Mask Register 2 (RXFPBM2)
      96. 8.6.96  Receive Pattern Byte Mask Register 3 (RXFPBM3)
      97. 8.6.97  Receive Pattern Byte Mask Register 4 (RXFPBM4)
      98. 8.6.98  Receive Pattern Control (RXFPATC)
      99. 8.6.99  10M SGMII Configuration (10M_SGMII_CFG)
      100. 8.6.100 I/O Configuration (IO_MUX_CFG)
      101. 8.6.101 GPIO Mux Control Register (GPIO_MUX_CTRL)
      102. 8.6.102 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      103. 8.6.103 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
      104. 8.6.104 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
      105. 8.6.105 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
      106. 8.6.106 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)
      107. 8.6.107 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)
      108. 8.6.108 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)
      109. 8.6.109 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)
      110. 8.6.110 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)
      111. 8.6.111 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)
      112. 8.6.112 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)
      113. 8.6.113 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)
      114. 8.6.114 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)
      115. 8.6.115 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)
      116. 8.6.116 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)
      117. 8.6.117 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)
      118. 8.6.118 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)
      119. 8.6.119 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)
      120. 8.6.120 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)
      121. 8.6.121 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)
      122. 8.6.122 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)
      123. 8.6.123 TDR General Status (TDR_GEN_STATUS)
      124. 8.6.124 Programmable Gain Register (PROG_GAIN)
      125. 8.6.125 MMD3 PCS Control Register (MMD3_PCS_CTRL)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Cable Line Driver
        2. 9.2.1.2 Clock In (XI) Recommendation
        3. 9.2.1.3 Crystal Recommendations
        4. 9.2.1.4 Clock Out (CLK_OUT) Phase Noise
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MAC Interface
          1. 9.2.2.1.1 SGMII Layout Guidelines
          2. 9.2.2.1.2 RGMII Layout Guidelines
        2. 9.2.2.2 Media Dependent Interface (MDI)
          1. 9.2.2.2.1 MDI Layout Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
    7. 12.7 Trademarks
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RGZ|48
サーマルパッド・メカニカル・データ
発注情報

Revision History

Changes from Revision C (October 2019) to Revision D (November 2022)

  • IEEE 1588 タイム・スタンプに対応する SOF(Start of Frame) 検出を更新Go
  • Updated Electrical CharacteristicsGo
  • Added Phy has internal 100 Ohm differential termination in Section 8.4.1.1 Go
  • Added following wording to the end of first paragraph in Section 8.4.3.9 "DP83867 devices manufactured after August, 2022, have an increased random seed value that now includes 255 different seed values to expedite Auto-MDIX resolution with a link partner."Go
  • Changed Bit 11:10 SPEED_OPT_ATTEMPT_CNT to RW description in Go
  • Changed bits 15:9, so that bit 12 can be '1'. Bit 7 description updated Section 8.6.31 Go
  • Added Register 0x008AGo
  • Added Register 0x00B3Go
  • Added Register 0x00C0Go
  • Added Register 0x0100Go

Changes from Revision B (March 2017) to Revision C (October 2019)

Changes from Revision A (February 2017) to Revision B (March 2017)

  • Changed pin 6 name in the pinout diagram from: VDDA1P0 to: VDD1P0Go
  • Changed INT / PWDN Interrupt descriptionGo
  • Changed RESERVED bit number from: 15:8 to: 15:9 Go
  • Changed RESERVED bit number from: 7 to: 8:7 Go
  • Changed the default and description of the CLK_O_DISABLE bit (bit 6)Go
  • Clarified Figure 9-2 Go
  • Changed text in MDI traces bullet from: or to: andGo

Changes from Revision * (October 2015) to Revision A (February 2017)

  • 最新のドキュメントおよび翻訳基準に合わせて、データシートのテキストを更新Go
  • Added storage temperature to Section 7.1 Go
  • Updated parameter symbol from VIH to VIH Go
  • Added MDC toggling clarification to Section 7.7 Go
  • Added Section 7.11 Go
  • Added DP83867IS/CS Start of Frame Detection TimingGo
  • Added section Section 8.3.2.1 Go
  • Changed target strap voltage thresholds Table 8-4 Go
  • Changed values for RX_CTRL pin for modes 1 and 2 to N/A in Table 8-5 Go
  • Changed strap name SPEED_SEL to ANEG_SEL in Table 8-5 Go
  • Changed table name Speed Select Strap Details to Auto-Negotiation Select Strap Details in Table 8-6 Go
  • Changed strap option SPEED_SEL to ANEG_SEL in Table 8-6 Go
  • Changed mode 5 RGMII Clock Skew value from 4.0 ns to 0 ns in Table 8-7 Go
  • Changed strap control of Speed Select bit 13 in Table 8-9 Go
  • Changed strap control of Speed Select bit 6 in Table 8-9 Go
  • Changed bit 9 name from 100BASE-T FULL DUPLEX to 1000BASE-T FULL DUPLEX in Table 8-18 Go
  • Changed bit 9 descriptions from half duplex to full duplex in Table 8-18 Go
  • Changed 'Interrupt Status and Event Control Register (ISR)' to 'MII Interrupt Control Register (MICR)' in Section 8.6.16 Go
  • Changed Register definition to move a statement from Section 8.6.17 to Section 8.6.16 Go
  • Changed default of bit 9 from '1' to '0' in Table 8-27 Go
  • Changed default of bits 5:0 from '0' to '0 0111' in Table 8-27 Go
  • Added Section 8.6.29 registerGo
  • Added Section 8.6.37 registerGo
  • Changed SPEED_SEL strap bit name to ANEG_SEL in Strap Configuration Status Register 1 (STRAP_STS1), Address 0x006EGo
  • Changed name of Bit 6:4 from 'STRAP_GMII_CLK_SKEW_TX' to 'STRAP_RGMII_CLK_SKEW_TX' in Table 8-48 Go
  • Changed name of Bit 6:4 from 'STRAP_GMII_CLK_SKEW_RX' to 'STRAP_RGMII_CLK_SKEW_RX' in Table 8-48 Go
  • Added Section 8.6.50 registerGo
  • Changed default of bits 12:8 to 0 1100 in Table 8-109 Go
  • Changed description for IO_IMPEDANCE_CTRL bits in Section 8.6.100 Go
  • Changed Section 10 sectionGo
  • Added power down supply sequence sentence in Section 10 Go
  • Added Figure 10-3 Go
  • Added Table 10-1 Go
  • Added note regarding 1.8-V supply sequence if no load exists on 2.5-V supply in Section 10 Go