JAJSSZ1 December   2023 DRV8334

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions 48-Pin DRV8334
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings DRV8334
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information DRV8334
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 SPI Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Three BLDC Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode
          2. 7.3.1.1.2 3x PWM Mode with INLx enable control
          3. 7.3.1.1.3 3x PWM Mode with SPI enable control
          4. 7.3.1.1.4 1x PWM Mode
          5. 7.3.1.1.5 SPI Gate Drive Mode
        2. 7.3.1.2 Gate Drive Architecture
          1. 7.3.1.2.1 Bootstrap diode
          2. 7.3.1.2.2 GVDD Charge pump
          3. 7.3.1.2.3 VCP Trickle Charge pump
          4. 7.3.1.2.4 Gate Driver Output
          5. 7.3.1.2.5 Passive and Semi-active pull-down resistor
          6. 7.3.1.2.6 TDRIVE Gate Drive Timing Control
          7. 7.3.1.2.7 Propagation Delay
          8. 7.3.1.2.8 Deadtime and Cross-Conduction Prevention
      2. 7.3.2 Low-Side Current Sense Amplifiers
        1. 7.3.2.1 Unidirectional Current Sense Operation
        2. 7.3.2.2 Bidirectional Current Sense Operation
      3. 7.3.3 Gate Driver Shutdown
        1. 7.3.3.1 DRVOFF Gate Driver Shutdown
        2. 7.3.3.2 Gate Driver Shutdown Timing Sequence
      4. 7.3.4 Gate Driver Protective Circuits
        1. 7.3.4.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.4.2  GVDD Undervoltage Lockout (GVDD_UV)
        3. 7.3.4.3  BST Undervoltage Lockout (BST_UV)
        4. 7.3.4.4  MOSFET VDS Overcurrent Protection (VDS_OCP)
        5. 7.3.4.5  VSENSE Overcurrent Protection (SEN_OCP)
        6. 7.3.4.6  Phase Comparators
        7. 7.3.4.7  Thermal Shutdown (OTSD)
        8. 7.3.4.8  Thermal Warning (OTW)
        9. 7.3.4.9  OTP CRC
        10. 7.3.4.10 SPI Watchdog Timer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
      2. 7.4.2 Device Power Up Sequence
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Format Diagrams
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application with 48-pin package
        1. 8.2.1.1 External Components
      2. 8.2.2 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply pin voltage PVDD -0.3 65 V
High-side MOSFET drain pin voltage VDRAIN -0.3 65 V
Voltage difference between ground pins AGND, GND -0.3 0.3 V
Charge pump pin voltage CPH -0.3 VGVDD + 0.3 V
Charge pump pin voltage CPL -0.3 VGVDD + 0.9 V
VPVDD + 0.6
Trickle Charge pump high-side pin voltage CPTH -0.3 80 V
Trickle Charge pump low-side pin voltage CPTL -0.3 VVDRAIN + 0.3 V
Trickle Charge pump output pin voltage VCP -0.3 80 V
Gate driver regulator pin voltage VGVDD GVDD -0.3 18 V
Logic pin voltage  nSLEEP -0.3 65 V
Logic pin voltage DRVOFF -0.3 65 V
Logic pin voltage INHx, INLx, nFAULT, SCLK, SDO, SDI, nSCS  -0.3 6.5 V
Logic pin voltage INHx, INLx, nFAULT, SCLK, SDO, SDI, nSCS : Transient -0.3 7.0 V
Bootstrap pin voltage BSTx, Continuous -0.3 80 V
BSTx with respect to SHx -0.3 20 V
BSTx with respect to GHx -0.3 20 V
Bootstrap pin transient current BSTx, Transient (500 ns), Assumed external component RBST = 2Ω and condition V(RBST) = -7V, 3.5 A
High-side gate drive pin voltage GHx, Continuous –8 80 V
High-side gate drive pin voltage GHx, Transient 1us –15 80 V
High-side gate drive pin voltage with respect to SHx GHx - SHx –0.3 BSTx + 0.3 V
High-side source pin voltage SHx, Continuous –8 70 V
High-side source pin voltage SHx, Transient 1us –15 72 V
Low-side gate drive pin voltage GLx with respect to SLx (LSS) -0.3 20 V
Low-side gate drive pin voltage GLx with respect to GVDD, VGVDD - VGLx 0.3 V
Low-side gate drive pin voltage GLx, Continuous -8 20 V
Low-side gate drive pin voltage GLx, Transient 1us -15 20 V
Low-side source sense pin voltage SLx, Continuous –8 VGVDD V
Low-side source sense pin voltage SLx, Transient 1us –15 VGVDD V
Gate drive current GHx, GLx Internally Limited Internally Limited A
Reference input pin voltage VREF –0.3 6 V
Shunt amplifier input pin voltage SNx, SPx, Continuous –5 5 V
Shunt amplifier input pin voltage SNx, SPx, Transient 1µs –15 15 V
Shunt amplifier output pin voltage SOx –0.3 VREF + 0.3 V
Power supply transient voltage ramp PVDD,  VDRAIN, VREF 3 V/µs
High-side source slew rate SHx, VBSTx - VSHx ≥ 5.5V
nSLEEP = High and ENABLE_DRV = 1b		 4 V/ns
Ambient temperature, TA Ambient temperature, TA –40 125 °C
Junction temperature, TJ Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime