JAJSRP0 October   2023 DS320PR410

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Shared Registers

Table 7-6 General Registers (Offset = 0xE2)
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6rst_i2c_regsR/W/SC0x0Device reset control: Reset all I2C registers to default values (self-clearing).
5-1RESERVEDR0x0Reserved
0frc_eeprm_rdR/W/SC0x0Override MODE and READ_EN_N status to force manual EEPROM configuration load.
Table 7-7 DEVICE_ID0 Register (Offset = 0xF0)
BitFieldTypeResetDescription
7-4RESERVEDR0x0Reserved
3device_id0_3R0x0Device ID0 [3:1]: 001
2device_id0_2R0x1see MSB
1device_id0_1R0x1see MSB
0RESERVEDRXReserved
Table 7-8 DEVICE_ID1 Register (Offset = 0xF1)
BitFieldTypeResetDescription
7device_id[7]R0x0Device ID 0010 1001: DS320PR410
6device_id[6]R0x0see MSB
5device_id[5]R0x1see MSB
4device_id[4]R0x0see MSB
3device_id[3]R0x1see MSB
2device_id[2]R0x0see MSB
1device_id[1]R0x0see MSB
0device_id[0]R0x0see MSB