SLYS021A January   2021  – May 2022 INA228

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (I2C)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Versatile High Voltage Measurement Capability
      2. 7.3.2 Internal Measurement and Calculation Engine
      3. 7.3.3 Low Bias Current
      4. 7.3.4 High-Precision Delta-Sigma ADC
        1. 7.3.4.1 Low Latency Digital Filter
        2. 7.3.4.2 Flexible Conversion Times and Averaging
      5. 7.3.5 Shunt Resistor Drift Compensation
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 Multi-Alert Monitoring and Fault Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
        1. 7.5.1.1 Writing to and Reading Through the I2C Serial Interface
        2. 7.5.1.2 High-Speed I2C Mode
        3. 7.5.1.3 SMBus Alert Response
    6. 7.6 Register Maps
      1. 7.6.1 INA228 Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current , Power, Energy, and Charge Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Input Filtering Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

I2C Serial Interface

The INA228 operates only as a secondary device on both the SMBus and I2C interfaces. Connections to the bus are made through the open-drain SDA and SCL lines. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although the device integrates spike suppression into the digital I/O lines, proper layout techniques help minimize the amount of coupling into the communication lines. This noise introduction could occur from capacitive coupling signal edges between the two communication lines themselves or from other switching noise sources present in the system. Routing traces in parallel with ground in between layers on a printed-circuit board (PCB) typically reduces the effects of coupling between the communication lines. Shielded communication lines reduce the possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start or stop commands.

The INA228 supports the transmission protocol for fast mode (1 kHz to 400 kHz) and high-speed mode (1 kHz to 2.94 MHz). All data bytes are transmitted most significant byte first and follow the SMBus 3.0 transfer protocol.

To communicate with the INA228, the main device must first address secondary devices through a secondary device address byte. The secondary device address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation.

The device has two address pins, A0 and A1. Table 7-2 lists the pin logic levels for each of the 16 possible addresses. The device samples the state of pins A0 and A1 on every bus communication. Establish the pin states before any activity on the interface occurs. When connecting the SDA pin to either A0 or A1 to set the device address, additional hold time of 100 ns is needed on the MSB of the I2C address to insure correct device addressing.

Table 7-2 Address Pins and Secondary Device Addresses
A1A0Secondary Device Address
GNDGND1000000
GNDVS1000001
GNDSDA1000010
GNDSCL1000011
VSGND1000100
VSVS1000101
VSSDA1000110
VSSCL1000111
SDAGND1001000
SDAVS1001001
SDASDA1001010
SDASCL1001011
SCLGND1001100
SCLVS1001101
SCLSDA1001110
SCLSCL1001111