JAJSID2F May   2011  – December 2019 LM5050-1 , LM5050-1-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      応用回路
      2.      代表的な冗長電源の構成
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM5050-1
    3. 6.3 ESD Ratings: LM5050-1-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IN, GATE, and OUT Pins
      2. 7.3.2 VS Pin
      3. 7.3.3 OFF Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 ON/OFF Control Mode
      2. 7.4.2 External Power Supply Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 MOSFET Selection
      2. 8.1.2 Short Circuit Failure of an Input Supply
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With Input and Output Transient Protection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Power Supply Components (R1 C1,) Selection
          2. 8.2.1.2.2 MOSFET (Q1) Selection
          3. 8.2.1.2.3 D1 and D2 Selection for Inductive Kick-Back Protection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Using a Separate VS Supply for Low Vin Operation
      3. 8.2.3 ORing of Two Power Sources
      4. 8.2.4 Reverse Input Voltage Protection With IQ Reduction
      5. 8.2.5 Basic Application With Input Transient Protection
      6. 8.2.6 48-V Application With Reverse Input Voltage (VIN = –48 V) Protection
        1. 8.2.6.1 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.1 MOSFET Selection

The important MOSFET electrical parameters are the maximum continuous Drain current ID, the maximum Source current (that is, body diode) IS, the maximum drain-to-source voltage VDS(MAX), the gate-to-source threshold voltage VGS(TH), the drain-to-source reverse breakdown voltage V(BR)DSS, and the drain-to-source On resistance RDS(ON).

The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The rating for the maximum current through the body diode, IS, is typically rated the same as, or slightly higher than the drain current, but body diode current only flows while the MOSFET gate is being charged to VGS(TH).

Gate Charge Time = Qg / IGATE(ON)

  1. The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage seen in the application. This would include any anticipated fault conditions.
  2. The drain-to-source reverse breakdown voltage, V(BR)DSS, may provide some transient protection to the OUT pin in low voltage applications by allowing conduction back to the IN pin during positive transients at the OUT pin.
  3. The gate-to-source threshold voltage, VGS(TH), should be compatible with the LM5050-1 gate drive capabilities. Logic level MOSFETs, with RDS(ON) rated at VGS(TH) at 5 V, are recommended, but sub-Logic level MOSFETs having RDS(ON) rated at VGS(TH) at 2.5 V, can also be used.
  4. The dominate MOSFET loss for the LM5050-1 active OR-ing controller is conduction loss due to source-to-drain current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by using a MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a MOSFET based solely on having low RDS(ON) may not always give desirable results for several reasons:
    1. Reverse transition detection. Higher RDS(ON) will provide increased voltage information to the LM5050-1 Reverse Comparator at a lower reverse current level. This will give an earlier MOSFET turnoff condition should the input voltage become shorted to ground. This will minimize any disturbance of the redundant bus.
    2. Reverse current leakage. In cases where multiple input supplies are closely matched it may be possible for some small current to flow continuously through the MOSFET drain to source (that is, reverse) without activating the LM5050-1 Reverse Comparator. Higher RDS(ON) will reduce this reverse current level.
    3. Cost. Generally, as the RDS(ON) rating goes lower, the cost of the MOSFET goes higher.
  5. The dominate MOSFET loss for the LM5050-1 active OR-ing controller is conduction loss due to source-to-drain current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by using a MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a MOSFET based solely on having low RDS(ON) may not always give desirable results for several reasons:
    1. Selecting a MOSFET with an RDS(ON) that is too large will result in excessive power dissipation. Additionally, the MOSFET gate will be charged to the full value that the LM5050-1 can provide as it attempts to drive the Drain to Source voltage down to the VSD(REG) of 22 mV typical. This increased Gate charge will require some finite amount of additional discharge time when the MOSFET needs to be turned off.
    2. As a guideline, it is suggest that RDS(ON) be selected to provide at least 22 mV, and no more than 100 mV, at the nominal load current.
    3. (22 mV / ID) ≤ RDS(ON) ≤ (100 mV / ID)
    4. The thermal resistance of the MOSFET package should also be considered against the anticipated dissipation in the MOSFET to ensure that the junction temperature (TJ) is reasonably well controlled, because the RDS(ON) of the MOSFET increases as the junction temperature increases.
  6. PDISS = ID2 × (RDS(ON))
  7. Operating with a maximum ambient temperature (TA(MAX)) of 35°C, a load current of 10 A, and an RDS(ON) of 10 mΩ, and desiring to keep the junction temperature under 100°C, the maximum junction-to-ambient thermal resistance rating (θJA) must be:
    1. RθJA ≤ (TJ(MAX) - TA(MAX))/(ID2 × RDS(ON))
    2. RθJA ≤ (100°C - 35°C)/(10 A × 10 A × 0.01 Ω)
    3. RθJA ≤ 65°C/W