JAJSRS8I February   2007  – November 2023 LM5116

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Performance Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High Voltage Start-Up Regulator
      2. 6.3.2 Enable
      3. 6.3.3 UVLO
      4. 6.3.4 Oscillator and Sync Capability
      5. 6.3.5 Error Amplifier and PWM Comparator
      6. 6.3.6 Ramp Generator
      7. 6.3.7 Current Limit
      8. 6.3.8 HO Output
      9. 6.3.9 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Soft-Start and Diode Emulation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design with WEBENCH® Tools
        2. 7.2.2.2  Timing Resistor
        3. 7.2.2.3  Output Inductor
        4. 7.2.2.4  Current Sense Resistor
        5. 7.2.2.5  Ramp Capacitor
        6. 7.2.2.6  Output Capacitors
        7. 7.2.2.7  Input Capacitors
        8. 7.2.2.8  VCC Capacitor
        9. 7.2.2.9  Bootstrap Capacitor
        10. 7.2.2.10 Soft Start Capacitor
        11. 7.2.2.11 Output Voltage Divider
        12. 7.2.2.12 UVLO Divider
        13. 7.2.2.13 MOSFETs
        14. 7.2.2.14 MOSFET Snubber
        15. 7.2.2.15 Error Amplifier Compensation
        16. 7.2.2.16 Comprehensive Equations
          1. 7.2.2.16.1 Current Sense Resistor and Ramp Capacitor
          2. 7.2.2.16.2 Modulator Transfer Function
          3. 7.2.2.16.3 Error Amplifier Transfer Function
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design with WEBENCH® Tools
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Typical limits are for TJ = 25°C only, represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only; minimum and maximum limits apply over the junction temperature range of –40°C to 125°C. Unless otherwise specified, the following conditions apply: VIN = 48 V, VCC = 7.4 V, VCCX = 0 V, EN = 5 V, RT = 16 kΩ, no load on LO and HO.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN SUPPLY
IBIAS VIN Operating Current VCCX = 0 V, VIN = 48 V 5 7 mA
VCCX = 0 V, VIN = 100 V 5.9 8
IBIASX VIN Operating Current VCCX = 5 V, VIN = 48 V 1.2 1.7 mA
VCCX = 5 V, VIN = 100 V 1.6 2.3
ISTDBY VIN Shutdown Current EN = 0 V, VIN = 48 V 1 10 µA
EN = 0 V, VIN = 100 V 1
VCC REGULATOR
VCC(REG) VCC Regulation 7.1 7.4 7.7 V
VCC LDO Mode Turnoff 10.6 V
VCC Regulation VIN = 6 V 5 5.9 6 V
VCC Sourcing Current Limit VCC = 0 V 15 26 mA
VCCX Switch Threshold VCCX Rising 4.3 4.5 4.7 V
VCCX Switch Hysteresis 0.25 V
VCCX Switch RDS(ON) ICCX = 10 mA 3.8 6.2 Ω
VCCX Leakage VCCX = 0 V –200 nA
VCCX Pull- down Resistance VCCX = 3 V 100 kΩ
VCC Undervoltage Threshold VCC Rising 4.3 4.5 4.7 V
VCC Undervoltage Hysteresis 0.2 V
HB DC Bias Current HB – SW = 15 V 125 200 µA
EN INPUT
VIL max EN Input Low Threshold 0.5 V
VIH min EN Input High Threshold 3.3 V
EN Input Bias Current VEN = 3 V –7.5 –3 1 µA
EN Input Bias Current VEN = 0.5 V –1 0 1 µA
EN Input Bias Current VEN = 100 V 20 90 µA
UVLO THRESHOLDS
UVLO Standby Threshold UVLO Rising 1.170 1.215 1.262 V
UVLO Threshold Hysteresis 0.1 V
UVLO Pull-up Current Source UVLO = 0 V 5.4 µA
UVLO Pull-down RDS(ON) 80 210 Ω
SOFT-START
SS Current Source SS = 0 V 8 11 14 µA
SS Diode Emulation Ramp Disable Threshold SS Rising 3 V
SS to FB Offset FB = 1.25 V 160 mV
SS Output Low Voltage Sinking 100 µA, UVLO = 0 V 45 mV
ERROR AMPLIFIER
VREF FB Reference Voltage Measured at FB pin, FB = COMP 1.195 1.215 1.231 V
FB Input Bias Current FB = 2 V 15 500 nA
COMP Sink/Source Current 3 mA
AOL DC Gain 80 dB
fBW Unity Gain Bandwidth 3 MHz
OSCILLATOR
fSW1 Frequency 1 RT = 16 kΩ 180 200 220 kHz
fSW2 Frequency 2 RT = 5 kΩ 480 535 590 kHz
RT output voltage 1.191 1.215 1.239 V
RT sync positive threshold 3 3.5 4 V
CURRENT LIMIT
VCS(TH) Cycle-by-cycle Sense Voltage Threshold (CSG - CS) VCCX = 0 V, RAMP = 0 V 94 110 126 mV
VCS(THX) Cycle-by-cycle Sense Voltage Threshold (CSG - CS) VCCX = 5 V, RAMP = 0 V 105 122 139 mV
CS Bias Current CS = 100 V –1 1(1) µA
CS Bias Current CS = 0 V 90 125 µA
CSG Bias Current CSG = 0 V 90 125 µA
RAMP GENERATOR
IR1 RAMP Current 1 VIN = 60 V, VOUT = 10 V 235 285 335 µA
IR2 RAMP Current 2 VIN = 10 V, VOUT = 10 V 21 28 35 µA
VOUT Bias Current VOUT = 36 V 200 µA
RAMP Output Low Voltage VIN = 60 V, VOUT = 10 V 265 mV
DIODE EMULATION
SW Zero Cross Threshold –6 mV
DEMB Output Current DEMB = 0 V, SS = 1.25 V 1.6 2.7 3.8 µA
DEMB Output Current DEMB = 0 V, SS = 2.8 V 28 38 48 µA
DEMB Output Current DEMB = 0 V, SS = Regulated by FB 45 65 85 µA
LO GATE DRIVER
VOLL LO Low-state Output Voltage ILO = 100 mA 0.08 0.17 V
VOHL LO High-state Output Voltage ILO = –100 mA, VOHL = VCC – VLO 0.25 V
IOHL Peak LO Source Current VLO = 0 V 1.8 A
IOLL Peak LO Sink Current VLO = VCC 3.5 A
HO GATE DRIVER
VOLH HO Low-state Output Voltage IHO = 100 mA 0.17 0.27 V
VOHH HO High-state Output Voltage IHO = –100 mA, VOHH = VHB – VHO 0.45 V
IOHH Peak HO Source Current VHO = 0 V 1 A
IOLH Peak HO Sink Current VHO = VCC 2.2 A
HB to SW undervoltage 3 V
THERMAL
TSD Thermal Shutdown Rising 170 °C
Thermal Shutdown Hysteresis 15 °C
(1) Specified at TJ = 25°C.