JAJSER7D November 2018 – January 2019 LMG1210
To properly drive the GaN FETs, TI recommends placing high-quality ceramic bypass capacitors as close as possible between the HB to HS and VDD to VSS. If using the LDO, the VDD-VSS capacitor is required to be at least 0.3 µF at bias for stability. However, a larger capacitor may be required for many applications.
The bootstrap capacitor must be large enough to support charging the high-side FET and supplying the high-side quiescent current when the high-side FET is on. The required capacitance can be calculated as Equation 7:
When using larger bootstrap capacitors, TI recommends that the VDD-VSS capacitor also be increased to keep the ratio at least 5 to 1. If this is not maintained, the charging of the bootstrap capacitor can pull the VDD-VSS rail down sufficiently to cause UVLO conditions and potentially unwanted behavior.