11.1 Layout Guidelines
The layout of the LMG1210 is critical for performance and functionality. The low inductance WQFN package helps mitigate many of the problems associated with board level parasitics, but take care with layout and placement with components to ensure proper operation. The following design rules are recommended.
- Place LMG1210 as close to the GaN FETs as possible to minimize the length of high-current traces between the HO/LO and the Gate of the GaN FETs
- Place bootstrap diode as close as possible to the LMG1210 to minimize the inductance of the BST to HB loop.
- Place the bypass capacitors across VIN to VSS, VDD to VSS, and HB to HS as close to the LMG1210 pins as possible. The VDD to VSS cap is a higher priority than the VIN to VSS cap.
- Separate power traces and signal traces, such as output and input signals, and minimize any overlaps between layers
- Minimize capacitance from the high-side pins to the input pins to minimize noise injection.