JAJSQD9B january   2015  – june 2023 LV2862

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Continuous Conduction Mode
      2. 7.3.2 Fixed Frequency PWM Control
      3. 7.3.3 Eco-mode
      4. 7.3.4 Bootstrap Voltage (CB)
      5. 7.3.5 Enable (SHDN) and VIN Undervoltage Lockout (UVLO)
      6. 7.3.6 Setting the Output Voltage
      7. 7.3.7 Current Limit
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Design Guide – Step By Step Design Procedure
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Switching Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Schottky Diode Selection
        5. 8.2.2.5 Input Capacitor Selection
          1. 8.2.2.5.1 Bootstrap Capacitor Selection
            1. 8.2.2.5.1.1 Typical Application Circuits
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Enable (SHDN) and VIN Undervoltage Lockout (UVLO)

The LV2862 SHDN pin is a high-voltage tolerant input with an internal pullup circuit. The device can be enabled even if the SHDN pin is floating. The regulator can also be turned on using 1.25 V or higher logic signals. It can be used if the use of a higher voltage is desired due to system or other constraints. A 100-kΩ or larger resistor is recommended between the applied voltage and the SHDN pin to protect the device. When SHDN is pulled down to 0 V, the chip is turned off and enters the lowest shutdown current mode. In shutdown mode, the supply current is decreased to approximately 1 µA. If the shutdown function is not to be used, the SHDN pin can be tied to VIN through a 100-kΩ resistor. The maximum voltage to the SHDN pin must not exceed 60 V. The LV2862 has an internal UVLO circuit to shut down the output if the input voltage falls below an internally fixed UVLO threshold level. This ensures that the regulator is not latched into an unknown state during low input voltage conditions. The regulator powers up when the input voltage exceeds the voltage level. If there is a requirement for a higher UVLO voltage, the SHDN pin can be used to adjust the input voltage UVLO by using external resistors.