JAJSSI0 December 2023 PCM3140-Q1
ADVANCE INFORMATION
The device supports the I2C control protocol as a target device, and is capable of operating in standard mode, fast mode, and fast mode plus. The I2C control protocol requires a 7-bit target address. The five most significant bits (MSBs) of the target address are fixed at 10011 and cannot be changed. The two least significant bits (LSBs) are programmable and are controlled by the ADDR0_SCLK and ADDR1_MISO pins. These two pins must always be either pulled to VSS or IOVDD. If the I2C_BRDCAST_EN (P0_R2_D2) bit is set to 1'b1, then the I2C target address is fixed to 1001100 in order to allow simultaneous I2C broadcast communication to all PCM3140-Q1 devices in the system. Table 7-48 lists the four possible device addresses resulting from this configuration.
ADDR1_MISO | ADDR0_SCLK | I2C_BRDCAST_EN (P0_R2_D2) | I2C TARGET ADDRESS |
---|---|---|---|
0 | 0 | 0 (default) | 1001 100 |
0 | 1 | 0 (default) | 1001 101 |
1 | 0 | 0 (default) | 1001 110 |
1 | 1 | 0 (default) | 1001 111 |
X | X | 1 | 1001 100 |