JAJSSI0 December 2023 PCM3140-Q1
ADVANCE INFORMATION
This regiser is the interrupt configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INT_POL | INT_EVENT[1:0] | Reserved | LTCH_READ_CFG | Reserved | |||
R/W-0h | R/W-0h | R-0h | R/W-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | INT_POL | R/W | 0h | Interrupt polarity. 0b = Active low (IRQZ) 1b = Active high (IRQ) |
6-5 | INT_EVENT[1:0] | R/W | 0h | Interrupt event configuration. 0d = INT asserts on any unmasked latched interrupts event 1d = Reserved 2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any unmasked latched interrupts event 3d = INT asserts for 2 ms (typical) one time on each pulse for any unmasked interrupts event |
4-3 | Reserved | R | 0h | Reserved |
2 | LTCH_READ_CFG | R/W | 0h | Interrupt latch registers readback configuration. 0b = All interrupts can be read through the LTCH registers 1b = Only unmasked interrupts can be read through the LTCH registers |
1-0 | Reserved | R | 0h | Reserved |