JAJSSI0 December 2023 PCM3140-Q1
ADVANCE INFORMATION
This register is the PDM DINx sampling edge configuration register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PDMDIN1_ EDGE | PDMDIN2_ EDGE | PDMDIN3_ EDGE | PDMDIN4_ EDGE | Reserved | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PDMDIN1_EDGE | R/W | 0h | PDMCLK latching edge used for channel 1 and channel 2 data. 0d = Channel 1 data are latched on the negative edge, channel 2 data are latched on the positive edge 1d = Channel 1 data are latched on the positive edge, channel 2 data are latched on the negative edge |
6 | PDMDIN2_EDGE | R/W | 0h | PDMCLK latching edge used for channel 3 and channel 4 data. 0d = Channel 3 data are latched on the negative edge, channel 4 data are latched on the positive edge 1d = Channel 3 data are latched on the positive edge, channel 4 data are latched on the negative edge |
5 | PDMDIN3_EDGE | R/W | 0h | PDMCLK latching edge used for channel 5 and channel 6 data. 0d = Channel 5 data are latched on the negative edge, channel 6 data are latched on the positive edge 1d = Channel 5 data are latched on the positive edge, channel 6 data are latched on the negative edge |
4 | PDMDIN4_EDGE | R/W | 0h | PDMCLK latching edge used for channel 7 and channel 8 data. 0d = Channel 7 data are latched on the negative edge, channel 8 data are latched on the positive edge 1d = Channel 7 data are latched on the positive edge, channel 8 data are latched on the negative edge |
3-0 | Reserved | R | 0h | Reserved |