JAJSC86B May   2016  – August 2016 REF6025 , REF6030 , REF6033 , REF6041 , REF6045 , REF6050


  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Solder Heat Shift
    2. 8.2 Thermal Hysteresis
    3. 8.3 Reference Droop Measurements
    4. 8.4 1/f Noise Performance
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Integrated ADC Drive Buffer
      2. 9.3.2 Temperature Drift
      3. 9.3.3 Load Current
      4. 9.3.4 Stability
    4. 9.4 Device Functional Modes
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Results
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報



10 Applications and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

Many applications, such as event-triggered and multiplexed data-acquisition systems, require the very first conversion of the ADC to have 18-bit or greater precision. These types of data acquisition systems capture data in bursts, and are also called burst-mode, data-acquisition systems. Achieving 18-bit precision for the first sample is very difficult using a conventional voltage reference because the voltage reference droop limits the accuracy of the first few conversions. Furthermore, variable-sampling-rate systems require that the gain error of the system does not vary with sampling rate. The primary objective of this design example is to demonstrate the lowest distortion and noise, burst-mode data-acquisition block with low power consumption, using an 18-bit SAR ADC operating at a throughput of 1 MSPS, for a 1-kHz, full-scale, pure sine-wave input.

10.2 Typical Application

REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 REF60xx_TIPD_BOS708.gif Figure 54. 18-bit, 1-MSPS, Burst-Mode Data Acquisition system

10.2.1 Design Requirements

  1. Burst-mode support (see Reference Droop Measurements section for more details)
  2. ENOB > 16 bits
  3. THD < –120 dB
  4. Power consumption < 50 mW
  5. Throughput = 1 MSPS

10.2.2 Detailed Design Procedure

The data acquisition system shown in Figure 54 has three major contributors to the noise and accuracy in the system: the input driver, the reference with driver, and the data converter. Each analog block is carefully designed so that the data converter specifications limit the system specifications. The THS4551, a fully differential operational amplifier is used to drive the 18-bit ADC (ADS8881). The charge-kickback RC filter at the output of the THS4551 is used to reduce the charge kickback created by the opening and closing of the sampling switch inside the ADC. Design the RC filter so that the voltage at the sampling capacitor settles to 18-bit accuracy within the acquisition time of the ADC.

Data-acquisition systems require stable and accurate voltage references in order to perform the most accurate data conversion. The REF60xx family of voltage references have integrated an ADC drive buffer, and can therefore drive the REF pin of the ADS8881 directly, without the need for an external reference buffer. See the Integrated ADC Drive Buffer section for more details about reference-buffer requirements. Correct output capacitor selection for the REF60xx is very important in this design. The Stability section describes the ESR requirements of the output capacitor for stability and burst-mode requirements. A capacitance of 1 μF is connected to the FILT pin to reduce broadband noise of the REF60xx. Results

Table 1 summarizes the measured results.

Table 1. Measured Results

SNR 100.5 dB
ENOB 16.4
THD –125.9 dB
Throughput 1 MSPS
Burst mode First sample > 18-bit precision
Power consumption 40 mW

10.2.3 Application Curves

REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 C024_SBOS708.png
REF6050 driving REF pin of ADS8881,
fIN = 1 kHz, SNR = 100.5 dB, THD = –125.9 dB
Figure 55. Typical FFT Plot
REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 C038_SBOS708.png
REF6050 driving REF pin of ADS8881,
fIN = 10 kHz, SNR = 99.2 dB, THD = –119.4 dB
Figure 57. Typical FFT Plot
REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 C047_SBOS708.png
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
positive full-scale input to ADS8881
Figure 59. Reference Droop
REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 C037_SBOS708.png
REF6050 driving REF pin of ADS8881,
fIN = 2 kHz, SNR = 100.4 dB, THD = –123.9 dB
Figure 56. Typical FFT Plot
REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 C049_SBOS708.png
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
AINP = AINN = VREF / 2 for ADS8881
Figure 58. Reference Droop
REF6025 REF6030 REF6033 REF6041 REF6045 REF6050 C048_SBOS708.png
REF6050 driving REF pin of ADS8881 operating at 1 MSPS,
negative full-scale input to ADS8881
Figure 60. Reference Droop