JAJSQG7 june   2023 SN75LVPE3410

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  9. 8Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.1.3 Application Curves

The SN75LVPE3410 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-compliant TX and RX are equipped with signal-conditioning functions and can handle channel losses of up to 22 dB at 4 GHz. With the SN75LVPE3410, the total channel loss between a PCIe root complex and an end point can be up to 32 dB at 4 GHz.

GUID-20230526-SS0I-XWWJ-JHC6-MDPG401DRKWG-low.svg Figure 8-4 Test Setup to Demonstrate PCIe 3.0 Link Reach Extension Using SN75LVPE3410 - (a) Baseline Setup, (b) With Redriver

Figure 8-4 shows a test setup to demonstrate reach extension capability of SN75LVPE3410 as PCIe 3.0 redriver. Table 8-1 provides the test results. As can be seen SN75LVPE3410 provide reach extension such a way that a PCIe 3.0 link with 34 dB total loss passes sigtest compliance requirements. Figure 8-5 shows eye diagram from PCIe 3.0 sigtest tool.

Table 8-1 PCIe 3.0 Link Reach Extension Using SN75LVPE3410
Setup Total Link Loss Minimum Eye Width Composite Eye Height PCIe 3.0 Sigtest Result
Baseline setup - no redriver 22 dB 62 ps 88 mV Pass
Link with redriver 34 dB 37 ps 141 mV Pass
GUID-20230526-SS0I-3LQ8-62SC-CV4TTT4S77JB-low.png Figure 8-5 PCIe 3.0 Sigtest Eye Diagram with 34 dB Total Loss Using SN75LVPE3410