JAJSQG7 june   2023 SN75LVPE3410

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  9. 8Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power
IACTIVE Device current consumption when all four channels are active All four channels enabled with VOD = L2, PWDN1, 2 = L 150 200 mA
IACTIVE-HALF Device current consumption when two channels are active Two channels enabled with VOD = L2, PWDN1 or PWDN2 = L 85 112 mA
ISTBY Device current consumption in standby power mode All four channels disabled, PWDN1, 2 = H 22 33 mA
VREG Internal regulator output 2.5 V
Control IO
VIH High level input voltage SDA, SCL, PWDN1, PWDN2 pins 2.1 V
VIL Low level input voltage SDA, SCL, PWDN1, PWDN2 pins 1.08 V
VOH High level output voltage Rpull-up = 100 kΩ (SDA, SCL pins) 2 V
VOL Low level output voltage IOL = –4 mA (SDA, SCL pins) 0.4 V
IIH Input high leakage current VInput = VDD, (SCL, SDA, PWDN1, PWDN2 pins) 10 µA
IIL Input low leakage current VInput = 0 V, (SCL, SDA, PWDN1, PWDN2 pins) -10 µA
CIN-CTRL Input capacitance 1.5 pF
4 Level IOs (EQ0_ADDR0, EQ1_ADDR1, EN_SMB, RX_DET, VOD, GAIN pins)
IIH_4L Input high leakage current, 4 level IOs VIN = 2.5 V 10 µA
IIL_4L Input low leakage current, 4 level IOs VIN = GND -150 µA
Receiver
ZRX-DC Rx DC Single-Ended Impedance 50 Ω
ZRX-DIFF-DC Rx DC Differential Impedance 100 Ω
Transmitter
ZTX-DIFF-DC DC Differential Tx Impedance Impedance of Tx during active signaling, VID, diff = 1Vpp 120 Ω
VTX-DC-CM Tx DC common mode Voltage 0.75 V
ITX-SHORT Tx Short Circuit Current Total current the Tx can supply when shorted to GND 90 mA