JAJSQG7 june   2023 SN75LVPE3410

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  9. 8Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
RLRX-DIFF Input differential return loss with minimal channel in TI evaluation board 50 MHz to 1.25 GHz -22 dB
1.25 GHz to 2.5 GHz -19 dB
2.5 GHz to 4.0 GHz -17 dB
RLRX-CM Input common-mode return loss with minimal channel in TI evaluation board 50 MHz to 2.5 GHz -18 dB
2.5 GHz to 4.0 GHz -13 dB
XTRX Receive-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent receiver pairs from 10 MHz to 4 GHz. -50 dB
GAIN CTLE block DC gain Ratio at GAIN = L3 and GAIN = L2, with low frequency CK 3.0 dB
Transmitter
VODL0-L2 Ratio of VOD gain L0 to L2 GAIN = L2, with low frequency CK -6 dB
VODL1-L2 Ratio of VOD gain L1 to L2 GAIN = L2, with low frequency CK -3.5 dB
VODL3-L2 Ration of VOD gain L3 to L2 GAIN = L2, with low frequency CK -1.5 dB
RLTX-DIFF Output differential return loss with minimal channel in TI evaluation board 50 MHz to 1.25 GHz -22 dB
1.25 GHz to 2.5 GHz -20 dB
2.5 GHz to 4.0 GHz -18 dB
RLTX-CM Output Common-mode return loss  with minimal channel in TI evaluation board 50 MHz to 2.5 GHz -13 dB
2.5 GHz to 4.0 GHz  -15 dB
XTTX Transmit-side pair-to-pair isolation Minimum pair-to-pair isolation (SDD21) between two adjacent transmitter pairs from 10 MHz to 4 GHz. -50 dB
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a channel Measured by observing propagation delay during either Low-to-High or High-to-Low transition 70 90 ps
LTX-SKEW Lane-to-Lane Output Skew Measured between any two lanes within a single transmitter 20 ps
EQGAIN4G High-frequencyuency EQ boost at 4 GHz Measured with maximum CTLE setting and maximum BW setting (EQ1 = L3, EQ0 = L3). Boost is defined as the gain at 4 GHz relative to 100 MHz. 12 dB
DCGAINVAR,max Maximum AC/DC gain variation VOD=L2, GAIN=L2, min EQ setting -2.5 2.5 dB
LINEARITY The output AC/DC linearity  VOD = L2.  800 mVpp