JAJSFJ0D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
---|---|---|---|---|---|---|---|---|---|
12 | 0x0C | RSV | RSV | RSV | RSV | RSV | RSV | RBCK | RLRK |
Reset Value | 0 | 0 |
RSV | Reserved | ||||||||
Reserved. Do not access. | |||||||||
RBCK | Master Mode BCK Divider Reset | ||||||||
This bit, when set to 0, will reset the SCK divider to generate BCK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. | |||||||||
Default value: 0 | |||||||||
0: Master mode BCK clock divider is reset | |||||||||
1: Master mode BCK clock divider is functional | |||||||||
RLRK | Master Mode LRCK Divider Reset | ||||||||
This bit, when set to 0, will reset the BCK divider to generate LRCK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly. | |||||||||
Default value: 0 | |||||||||
0: Master mode LRCK clock divider is reset | |||||||||
1: Master mode LRCK clock divider is functional |